Senior RTL Design Architect, IO & Memory Systems

Showcify; Austin, San Jose (TX, CA); On-site; USD 180,000 - 255,000; Full time

Benefits offered by this job

Health insurance

Dental & Vision

HSAs and utilities

Job summary

SambaNova Systems is seeking a Principal Engineer to own the design, integration, and implementation of high‑speed IO and memory subsystems within the DataScale platform. Lead architecture exploration, RTL development, and cross‑functional collaboration to deliver scalable AI infrastructure.

You will drive microarchitecture, IP selection, and end‑to‑end validation for PCIe, Ethernet, HBM, and CXL interfaces, working with software, firmware, and STA teams while maintaining strong ownership and

Qualifications

• Clear and effective communicator with a proactive, collaborative approach to problem‑solving.
• MS in Electrical Engineering, Computer Science, or a related field.
• 7+ years of experience in ASIC design.
• Experience with SystemVerilog RTL design and functional verification.
• Experience with memory subsystems such as HBM and CXL.
• Familiarity with PCIe, Ethernet, AXI, UCIe interfaces.

Responsibilities

• Engage in architecture exploration with system and chip architects to define IO and memory subsystem direction.
• Drive feasibility studies and design trade‑off analysis to meet PPA constraints.
• Own microarchitecture definition and specification for IO and memory subsystems.
• Deliver synthesizable, high‑quality SystemVerilog RTL for assigned blocks against functionality, performance, and power targets.
• Run the front‑end design flow end to end, covering lint, CDC/RDC, synthesis, timing constraint development, and design‑for‑test readiness.
• Partner with STA and physical design teams on timing closure, floorplanning, congestion analysis, and optimization at advanced process nodes.
• Work closely with verification and emulation teams to ensure design validation coverage and quality.
• Collaborate with software and firmware teams to ensure optimal end‑to‑end solutions.
• Drive cross‑functional triage of complex functional and performance issues to root cause and closure.
• Apply engineering best practices including code review, testing, and refactoring.
• Improve design and integration methodology, reuse, and flow scalability.

Skills

Clear communicator

Collaborative

Education

MS in Electrical Engineering or Computer Science

Tools

SystemVerilog RTL design

Functional verification

PCIe

HBM

CXL

AXI / Ethernet / UCIe

Job description

SambaNova Systems is seeking a Principal Engineer to own the design, integration, and implementation of high‑speed IO and memory subsystems within the DataScale platform. Lead architecture exploration, RTL development, and cross‑functional collaboration to deliver scalable AI infrastructure.

You will drive microarchitecture, IP selection, and end‑to‑end validation for PCIe, Ethernet, HBM, and CXL interfaces, working with software, firmware, and STA teams while maintaining strong ownership and