Principal RTL Lead – High Speed Ethernet (ASIC)

MosChip®; Santa Clara (CA); On-site; USD 150,000 - 200,000; Full time

Job summary

A semiconductor design company is seeking a Principal RTL Lead to drive the development of next-generation Ethernet subsystems. This role involves defining architecture for ultra-fast data centers and leading a team in implementing high-speed Ethernet IP. Candidates must have over 10 years of experience in RTL design and a strong background in Ethernet protocols. The position offers a contract duration of 6+ months in the Bay Area, California, with a work week from Monday to Friday.

Qualifications

• 10+ years of experience in RTL design with 3-4 successful tape-outs in advanced process nodes.
• Deep experience with 100G/400G/800G Ethernet protocols and the underlying sub-layers.
• Expert knowledge of full front-end ASIC flow from architectural spec to post-silicon bring-up.

Responsibilities

• Act as the primary architect for the Ethernet subsystem and define micro-architecture.
• Own the implementation of IEEE 802.3 standards and manage massive bus widths.
• Lead the integration of third-party SerDes IP and ensure seamless interoperability.

Skills

RTL design

Ethernet protocols

SystemVerilog

Python

Job description

Company Overview

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

Job Summary

We are seeking a seasoned Principal RTL Lead to spearhead the development of next‑generation Ethernet subsystems. This isn’t just about moving packets; it’s about defining the architecture for 400G, 800G, and beyond. As the technical lead, you will own the logic that powers the world’s fastest data centers, ensuring ultra‑low latency and rock‑solid reliability at massive scale.

Candidate will lead a high‑caliber team of designers to implement high‑speed Ethernet IP (MAC/PCS/PMA) into our custom ASIC silicon. Your role is a blend of deep technical execution and strategic mentorship—steering the team through the complexities of multi‑lane alignment, Forward Error Correction (FEC), and high‑speed clocking challenges.

Key Responsibilities

• Act as the primary architect for the Ethernet subsystem, defining micro‑architecture for high‑bandwidth data paths and complex control logic.
• Own the implementation of IEEE 802.3 standards, including RS‑FEC (254, 256), multi‑lane distribution (MLD), and auto‑negotiation/link training (AN/LT).
• Solve the hard problems of networking: managing massive bus widths (e.g., 1024‑bit+), minimizing logic depth for timing closure, and handling complex CDC across asynchronous boundaries.
• Lead the integration of third‑party SerDes IP and ensure seamless interoperability between the electrical physical layer and the digital MAC.
• Drive best practices in coding (SystemVerilog), power optimization (UPF), and lint/CDC/RDC analysis to ensure first‑pass silicon success.

Qualifications

• 10+ years of experience in RTL design with at least 3-4 successful tape‑outs in advanced process nodes (7nm, 5nm, or 3nm).
• Deep, hands‑on experience with 100G/400G/800G Ethernet protocols and the underlying sub‑layers (MAC, PCS, FEC).
• Expert knowledge of the full front‑end ASIC flow—from architectural spec to synthesis, formal verification, and post‑silicon bring‑up.
• Proven ability to close timing on high‑frequency designs and manage complex clocking architectures.
• Proficiency in Python or Perl for creating sophisticated design‑generation and analysis tools.
• Desirable skills: Experience with IEEE 1588 (PTP) hardware stamping for precision timing; familiarity with CXL or PCIe Gen 5/6 protocols; direct experience working with physical design teams on timing and congestion mitigation.

Experience: 10+ Years

Location: Bay Area, California

Contract Duration: 6+ months

Shift: General

Work Week: Monday to Friday

Contact: www.moschip.com