RTL Design Engineer – Interconnect & Network Datapath

OpenAI; United States; Remote; USD 180,000 - 280,000; Full time

Job summary

OpenAI’s Hardware organization seeks a highly experienced RTL engineer with deep packet-networking and interconnect expertise to own critical on‑chip communication components for our AI accelerator platform.

You will drive the microarchitecture, RTL implementation, and verification closure, coordinating silicon bring‑up and production readiness while mentoring junior engineers and coordinating with external partners.

Qualifications

• Senior RTL engineer with packet-networking and interconnect expertise.
• Owned production RTL for networking datapaths such as Ethernet switches, NICs, or NoCs.
• Experience driving microarchitecture, SystemVerilog implementation, verification closure, and silicon bring-up.

Responsibilities

• Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components (NoC fabrics, switches, routers, bridges, advisory components).
• Plan and oversee the work of junior engineers and foster productive relationships with external partners.
• Lead designs from requirements through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, and production readiness.

Skills

RTL design

SystemVerilog

Packet-networking

NoC fabrics

Microarchitecture

Verification

Silicon bring-up

Leadership

Job description

About the Team

OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform.

About the Role

We are looking for a highly experienced, hands‑on RTL engineer with deep packet‑networking and interconnect expertise to own critical on‑and off‑chip communication components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on‑chip fabrics connecting high‑bandwidth compute, memory, and I/O subsystems, as well as purpose‑built off‑chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet‑switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale‑up/scale‑out fabrics. This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring‑up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners.

In this role, you will:

• Own the microarchitecture, RTL design, and delivery of major packet‑based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic‑management logic.
• Design mechanisms for routing, arbitration, ordering, flow con