Senior RTL Design Engineer - Crafting Custom Silicon & IP

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google in Mountain View, CA is seeking a Senior Design Engineer, RTL to drive RTL development and IP integration for cutting-edge silicon solutions powering consumer products.

The role emphasizes deep expertise in ASIC design, Verilog/VHDL, and microarchitecture. You will collaborate with multi-site teams to deliver high-performance, power-efficient hardware with strong validation and verification practices.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 8 years of experience with IP Development or Integration.
• Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language).

Responsibilities

• Define microarchitecture specifications for silicon subsystems and IP blocks to meet performance, area, and power.
• Integrate IP blocks into complex silicon designs and multi-component subsystems.
• Perform production RTL coding, debug, lint, CDC, formal verification, and UPF checks.
• Collaborate with validation teams on test plans and coverage for design verification.
• Drive alignment across multidisciplinary teams to ensure on-time product delivery.

Skills

IP Development Experience

ASIC Design

RTL Coding

Verilog/VHDL

Education

Bachelor's Degree

Tools

Verilog

VHDL

Job description

Google in Mountain View, CA is seeking a Senior Design Engineer, RTL to drive RTL development and IP integration for cutting-edge silicon solutions powering consumer products.

The role emphasizes deep expertise in ASIC design, Verilog/VHDL, and microarchitecture. You will collaborate with multi-site teams to deliver high-performance, power-efficient hardware with strong validation and verification practices.