Senior ASIC RTL Design Engineer for Cutting-Edge SoCs

Infobahn Softworld Inc; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Infobahn Softworld Inc in San Jose, CA is seeking an experienced RTL Design Engineer to help design leading edge SoCs in advanced CMOS processes. You'll contribute across architecture, micro-architecture, verification, and timing closure to deliver silicon.

The ideal candidate has hands-on ASIC flow experience, RTL coding, and familiarity with ARM cores and IO interfaces, plus strong communication, documentation, and technical leadership to guide cross-functional teams.

Qualifications

• SoC design experience in ASIC flow including RTL coding, debugging/verification, and supporting synthesis and timing closure.
• Experience with ARM cores and IO interfaces.
• Strong communication, documentation, time management, and leadership abilities.

Responsibilities

• Lead and participate in the design of leading edge SoCs in advanced digital CMOS processes.
• Contribute to chip definition, architecture development, and micro-architectural specs.
• Convert micro-architectural specs to logic implementation, verification, emulation, debug, synthesis, and timing closure.
• Interface with physical execution, software, and silicon bring-up teams.

Skills

SoC Architecture

ASIC design

RTL coding

timing closure

ARM cores

I/O interfaces

Communication skills

Documentation skills

Time management

Technical leadership

Job description

Infobahn Softworld Inc in San Jose, CA is seeking an experienced RTL Design Engineer to help design leading edge SoCs in advanced CMOS processes. You'll contribute across architecture, micro-architecture, verification, and timing closure to deliver silicon.

The ideal candidate has hands-on ASIC flow experience, RTL coding, and familiarity with ARM cores and IO interfaces, plus strong communication, documentation, and technical leadership to guide cross-functional teams.