Integration RTL Design Engineer

Advanced Micro Devices, Inc.; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

Advanced Micro Devices, Inc. is seeking a Senior ASIC Design Engineer for their Silicon Design team in San Jose, CA. The role involves owning the complete RTL design lifecycle and working on complex IP design for next-generation embedded products.

Candidates should have deep expertise in Verilog RTL coding and experience with the entire ASIC development process, including timing closure and SOC integration. The role promotes mentoring junior engineers and leading projects to successful completion.

Qualifications

• Proven experience across the entire chip development lifecycle.
• Deep technical expertise with multiple production tape-outs.
• Experience integrating complex ASIC IP blocks into SOC designs.

Responsibilities

• Own complete RTL design lifecycle from micro-architecture to production silicon.
• Drive full ASIC development lifecycle including timing analysis and verification.
• Collaborate with physical design to achieve timing closure.

Skills

Verilog RTL coding

Timing closure

Physical design awareness

Scripting languages (Python/Perl/Tcl)

Education

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

Tools

PrimeTime

Tempus

Job description

THE ROLE

Join AMD's Silicon Design team to design and develop cutting‑edge IPs for next‑generation embedded products. As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro‑architecture specification through production silicon, working on complex IP design.

THE PERSON

The ideal candidate is a seasoned ASIC/SOC designer with proven expertise across the entire chip development lifecycle—from RTL design through silicon bring‑up. You excel in Verilog RTL coding, timing closure, and physical design awareness. With multiple production tape‑outs under your belt, you bring deep technical expertise, strong ownership, and the ability to mentor junior engineers while driving projects to successful completion.

KEY RESPONSIBILITIES

• RTL Design & Microarchitecture: Author detailed micro‑architecture specifications and own complete Verilog RTL implementation of major IP blocks, ensuring compliance with PPA (Performance, Power, Area) targets and timing requirements.
• Full ASIC Development Lifecycle: Drive design from concept through production silicon across all phases: specification, RTL coding, lint/CDC checks, synthesis, timing analysis, verification, physical design integration, and post‑silicon validation.
• Timing Closure & Optimization: Develop and maintain timing constraints (SDC), perform static timing analysis (STA) using industry‑standard tools (PrimeTime/Tempus), resolve timing violations, and collaborate with physical design to achieve timing closure.
• SOC Integration: Integrate complex ASIC IP blocks into full‑chip SOC environment, ensuring proper connectivity, clock domain crossings, and interface compliance with industry‑standard protocols (AMBA AXI/AHB/APB, PCIe, CXL).
• Design Quality & Verification: Partner with verification teams to ensure comprehensive functional coverage; implement design‑for‑test (DFT) and design‑for‑debug (DFD) features; participate in RTL quality reviews and signoff.
• Physical Design Collaboration: Work closely with physical design engineers on floorplanning, placement constraints, clock tree synthesis, and power grid design to ensure timing convergence and manufacturing readiness.
• Automation & Productivity: Develop Python/Perl/Tcl scripts to automate repetitive tasks, improve design quality checks, and enhance team efficiency throughout the design flow.
• Cross‑Functional Collaboration: Engage with architecture, verification, physical design, CAD, and post‑silicon teams to resolve complex technical challenges and deliver high‑quality silicon on schedule.

PREFERRED EXPERIENCE

• Proven track record with 2+ production ASIC tape‑outs in senior design roles.
• Verilog RTL coding skills with deep understanding of synthesizable RTL constructs and coding best practices.
• Hands‑on experience with the complete ASIC design flow: RTL Synthesis STA Physical Design Tape‑out.
• Experience writing and debugging SDC timing constraints, including multi‑cycle paths, false paths, and clock domain crossing constraints.
• Experience integrating complex IP blocks into SOC designs.
• Knowledge of industry‑standard on‑chip interconnect protocols (AMBA AXI/AHB/APB).
• Knowledge of ARM architecture and AMBA protocol specifications.
• Experience with low‑power design techniques (clock gating, power gating, voltage scaling).
• Proficiency in scripting languages: Python, Perl, Tcl, or Shell scripting.
• Exposure to formal verification tools for equivalence checking and property verification.
• Familiarity with AI‑assisted design tools and modern EDA technologies.
• Experience mentoring junior engineers and leading design teams.
• Strong technical writing skills for design specifications and documentation.
• Excellent communication and collaboration skills in cross‑functional environments.

ACADEMIC QUALIFICATIONS

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.

LOCATION

San Jose, CA

IMPORTANT INFORMATION

This role is not eligible for visa sponsorship.

EEO STATEMENT

AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.