Senior RTL Design Engineer – Low-Power SoC & IP Integration

Apple; San Diego (CA); On-site; USD 157,000 - 214,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock programs

Relocation assistance

Tuition reimbursement

Job summary

Apple Inc. in San Diego, CA is offering a role focused on microarchitecture definition and RTL design using SystemVerilog/Verilog. Responsibilities include IP integration, verification, and timing analysis with a strong emphasis on low-power design and multi-clock-domain issues.

Collaboration with firmware and system teams is essential. Applicants should hold a Master's degree in Electrical/ Electronics/ Communications engineering or related field, with 3 years of applicable experience, and

Qualifications

• Master's degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Communication Engineering, or a related field and 3 years of experience in the job offered or related occupation.
• Experience with SystemVerilog/Verilog RTL for high-speed IPs.
• Experience automating RTL integration, verification, synthesis and timing analysis with scripting languages.
• Experience with CDC/RDC tools and multi-clock/domain designs.
• RTL design experience with complex FSMs and power-saving features.
• IP integration including clock/reset modules, clock gating, fabric/bus configuration.
• Knowledge of low-power design concepts including clock/power gating and DVFS.
• Knowledge of high-speed interfaces (AXI/AHB) and related peripherals.
• Experience with Synthesis tools from Synopsys and Cadence; setting constraints; knowledge of LEC/LEQ.
• Understanding of computer architecture and SOCs; wireless communications knowledge.

Responsibilities

• Define and implement RTL for high-speed IP blocks
• Integrate IP modules including clock/reset and clock gating
• Perform verification, synthesis and timing analysis using automation scripts
• Collaborate with system/algorithm and firmware teams to optimize performance and power
• Apply low-power design techniques including DVFS, clock gating and power gating
• Ensure lint-free and CDC-clean RTL designs and manage multiple clock domains

Skills

SystemVerilog/Verilog RTL design

Python/Perl/TCL scripting

CDC/RDC concepts

Clock domain management

IP integration

Low power design (clock gating, power/

AXI/AHB interfaces

Education

Master's degree in Electrical/Electronics/Communications engineering or related field

Tools

Synopsys tools

Cadence tools

LEC/LEQ

Job description

Apple Inc. in San Diego, CA is offering a role focused on microarchitecture definition and RTL design using SystemVerilog/Verilog. Responsibilities include IP integration, verification, and timing analysis with a strong emphasis on low-power design and multi-clock-domain issues.

Collaboration with firmware and system teams is essential. Applicants should hold a Master's degree in Electrical/ Electronics/ Communications engineering or related field, with 3 years of applicable experience, and