GPU Power & RTL Design Engineer — SoC/IP Integration

The Briefed; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Apple in Austin is seeking a senior RTL engineer to design and optimize RTL for GPU power management and SoC interface logic. You will collaborate with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications, integrate IP, and drive performance, power, and area goals across multi-site teams.

The role requires a BS in EE, CE, or ECE, strong Verilog/SystemVerilog RTL experience, and scripting skills.

Qualifications

• BS in EE, CE, or ECE.
• Experience in logic optimization, synthesis, timing analysis, floor-planning, power intent descriptions, and clock domain crossings.
• Experience writing RTL in Verilog and/or SystemVerilog; experience with logic simulation and debug.

Responsibilities

• Deliver RTL design collateral, including RTL, to Physical Design teams.
• Assess and integrate IP from other Apple teams.
• Close timing, power, area, and lint by optimizing RTL and constraints.
• Drive performance, power, area, and functional goals.
• Provide schedules to IP teams and management.
• Collaborate with IP teams across multiple sites.

Skills

RTL design

Verilog

SystemVerilog

Logic optimization

Synthesis

Timing analysis

Floor-planning

Power integrity

Clock domain crossings

IP integration

Scripting languages

Education

BS in EE, CE, or ECE

Job description

Apple in Austin is seeking a senior RTL engineer to design and optimize RTL for GPU power management and SoC interface logic. You will collaborate with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications, integrate IP, and drive performance, power, and area goals across multi-site teams.

The role requires a BS in EE, CE, or ECE, strong Verilog/SystemVerilog RTL experience, and scripting skills.