Senior RTL & DSP Design Engineer - Mixed-Signal Silicon

Apple Inc.; Irvine (CA); On-site; USD 175,000 - 309,000; Full time

Benefits offered by this job

Comprehensive medical and dental

Retirement benefits

Discounted products and free services

Tuition reimbursement

Discretionary bonuses or relocation

Job summary

Apple is seeking a results-oriented RTL Design Engineer in Irvine, CA to join the mixed-signal silicon design team. You will specify, design, verify, and support lab bring-up of digital and mixed-signal blocks and help integrate high-performance IPs into silicon.

The role emphasizes Verilog/SystemVerilog RTL coding, DSP algorithm translation, and collaboration across analog, verification, and system architects.

Qualifications

• BS with at least 10 years of relevant industry experience.

Responsibilities

• Develop RTL code in Verilog/SystemVerilog for mixed-signal digital blocks and DSP pipelines.
• Translate DSP concepts into efficient RTL implementations.
• Write comprehensive assertions and unit-level testbenches for verification.
• Partner with cross-functional teams to integrate IPs and support lab bring-up.
• Collaborate with analog designers, verification engineers, and system architects.

Skills

RTL design

Verilog/SystemVerilog

DSP concepts

Design verification

System integration

Education

Bachelor's degree in electrical engineering

Tools

Verilog simulators

linters

CDC checkers

Job description

Apple is seeking a results-oriented RTL Design Engineer in Irvine, CA to join the mixed-signal silicon design team. You will specify, design, verify, and support lab bring-up of digital and mixed-signal blocks and help integrate high-performance IPs into silicon.

The role emphasizes Verilog/SystemVerilog RTL coding, DSP algorithm translation, and collaboration across analog, verification, and system architects.