ASIC/SoC RTL Design Engineer — NoC, Coherence & Power

Apple; Santa Clara (CA); Presencial; USD 129.000 - 195.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical and dental coverage

Retirement benefits

Employee stock programs

Education reimbursement

Descripción de la vacante

Apple, Inc. seeks a design engineer to own RTL development within a high-performance SoC team in Santa Clara, CA.

You will design and integrate coherent and non-coherent fabrics, work with front-end teams to hit timing, and collaborate across multi-disciplinary groups to deliver high-quality blocks. Qualifications include a BS degree and experience with NoC architectures, memory hierarchies, and collaboration with synthesis, power, and verification teams.

Formación

• BS in related field required.
• Experience with RTL design tools preferred.
• Knowledge of NoC architectures and memory hierarchy.

Responsabilidades

• Design and integration of coherent and non-coherent fabrics into a subsystem or SoC with NoC topology.
• Own RTL development design, templating, scripting and RTL generation.
• Collaborate with other designers to deliver results.
• Integrate shared IP blocks to design and optimize memories/hard macros.
• Work with front-end synthesis/STA teams to ensure timing for the block is met.
• Coordinate with power/performance and verification teams to ensure quality.
• Collaborate across multi-disciplinary groups to deliver on time with proper checks.

Conocimientos

Interpersonal skills

Self-motivated

Highly organized

Schedule driven

Collaborative mindset

Educación

Bachelor's degree in Electrical Engineering or related field

Herramientas

lint

CDC

Synthesis

Descripción del empleo

Apple, Inc. seeks a design engineer to own RTL development within a high-performance SoC team in Santa Clara, CA.

You will design and integrate coherent and non-coherent fabrics, work with front-end teams to hit timing, and collaborate across multi-disciplinary groups to deliver high-quality blocks. Qualifications include a BS degree and experience with NoC architectures, memory hierarchies, and collaboration with synthesis, power, and verification teams.