Senior Digital Design Engineer — DRAM RTL & PPA Expert

Micron Technology, Inc; Boise (ID); Hybrid; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off

Paid holidays

Job summary

Micron Technology in Boise, Idaho is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. The role covers RTL design, implementation, synthesis, timing analysis, and power optimization across the RTL-to-GDS flow, working with architecture, verification and physical design teams to meet stringent product specifications and PPA targets.

This position emphasizes collaboration, innovation, and quality, with opportunities to

Qualifications

• Master’s degree in Electrical Engineering or equivalent with 4+ years in digital ASIC/RTL design.
• Experience developing RTL for complex digital designs from spec through handoff.
• Strong knowledge of ASIC front-end design flows: RTL, verification, synthesis, STA.
• Experience with design constraints (SDC), clocks, timing exceptions, and multi-mode timing.
• Proficiency with Verilog/SystemVerilog and industry-standard simulation tools.
• Experience with UPF-based low-power design and PPA optimization.

Responsibilities

• Design, develop, and deliver RTL for complex DRAM digital and mixed-signal blocks.
• Perform linting, CDC/RDC analysis, logic synthesis, timing constraint development, and timing closure.
• Collaborate with architecture, verification, and physical design teams to optimize PPA.
• Develop and maintain synthesis and timing constraints (SDC) and drive timing closure.
• Improve design methodologies, automation, and RTL-to-GDS flow.

Skills

RTL design

Verilog/SystemVerilog

Power optimization

PPA optimization

STA / timing analysis

Education

Master’s degree in Electrical Engineering

Bachelor’s degree in Electrical Engineering

Tools

Industry-standard simulation tools

Job description

Micron Technology in Boise, Idaho is seeking a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks. The role covers RTL design, implementation, synthesis, timing analysis, and power optimization across the RTL-to-GDS flow, working with architecture, verification and physical design teams to meet stringent product specifications and PPA targets.

This position emphasizes collaboration, innovation, and quality, with opportunities to