Senior Digital Design Engineer: High-Performance DRAM RTL

Micron Technology; Boise (ID); On-site; USD 120,000 - 160,000; Full time

Job summary

Micron Technology in Boise, Idaho seeks a Senior Digital Design Engineer to contribute to the RTL-to-GDS flow for next‑gen DRAM digital and mixed-signal blocks. You will design RTL, perform synthesis, timing analysis, and power optimization to meet product specifications and PPA targets.

The role collaborates with architecture, verification and physical design teams to deliver high-performance, power-efficient designs and drive time-to-market.

Qualifications

• Master’s degree with 4+ years of experience or Bachelor’s with 5+ years in digital ASIC/RTL design.
• Proven RTL development experience from specification through implementation handoff.
• Strong knowledge of front-end ASIC design flows: RTL, verification, synthesis, STA.
• Experience creating and maintaining design constraints (SDC) with clocks and multi‑mode timing.
• Proficiency with Verilog/SystemVerilog and industry-standard simulation tools.
• Experience with UPF-based power intent and PPA optimization.

Responsibilities

• Design, develop, and deliver RTL for complex DRAM digital/mixed-signal blocks.
• Perform linting, CDC/RDC analysis, synthesis, timing constraints, and timing closure.
• Collaborate with architecture, verification, and physical design teams to optimize PPA.
• Maintain synthesis and timing constraints (SDC) and drive timing closure across scenarios.
• Improve RTL methodologies, automation, and RTL-to-GDS flow for efficiency.

Skills

RTL design

Verilog/SystemVerilog

STA

CDC/RDC analysis

Synthesis

PPA optimization

Education

Master’s degree in Electrical Engineering

Bachelor’s degree in Electrical Engineering

Tools

Simulation tools

Job description

Micron Technology in Boise, Idaho seeks a Senior Digital Design Engineer to contribute to the RTL-to-GDS flow for next‑gen DRAM digital and mixed-signal blocks. You will design RTL, perform synthesis, timing analysis, and power optimization to meet product specifications and PPA targets.

The role collaborates with architecture, verification and physical design teams to deliver high-performance, power-efficient designs and drive time-to-market.