SR RTL DESIGN

Micron Technology, Inc; Boise (ID); On-site; USD 100,000 - 130,000; Full time

Job summary

Micron Technology, Inc is seeking a Senior RTL Engineer in Boise, Idaho, to develop DRAM digital and mixed-signal blocks. The successful candidate will support the RTL lifecycle and collaborate with multi-functional teams to create high-quality designs that meet power, performance, and area targets.

Key qualifications include a Master's degree in Electrical Engineering or a Bachelor's with significant RTL experience, strong skills in ASIC design flows, and proficiency in Verilog/SystemVerilog. This position offers a dynamic and innovative engineering environment.

Qualifications

• Master’s degree in Electrical Engineering with 4+ years of experience, or Bachelor’s with 5+ years of RTL design.
• Experience developing RTL for complex digital IP.
• Strong knowledge of ASIC design flows and static timing analysis.

Responsibilities

• Contribute to RTL build of digital and mixed-signal components for DRAM.
• Implement high-performance, power- and area-efficient RTL designs.
• Collaborate with physical design teams to achieve timing closure.

Skills

RTL design

Verilog/SystemVerilog

ASIC design flows

Power design methodologies

Education

Master’s in Electrical Engineering or Bachelor's with 5+ years pre-silicon RTL design

Tools

RTL simulation tools

Job description

Job Summary

At Micron Technology, we are looking for a Senior RTL Engineer to build and develop DRAM digital and mixed‑signal blocks for advanced memory products. In this role, you will support the RTL lifecycle from specification and implementation to signoff. You will collaborate with multi‑functional teams to develop high‑quality builds that meet power, performance, and area (PPA) targets. This position is based in Boise, Idaho, within a collaborative and innovative engineering environment.

Responsibilities

• Contribute to RTL build of digital and mixed‑signal components for DRAM using RTL‑to‑GDS flows.
• Implement and document high‑performance, power‑ and area‑efficient RTL designs meeting product specifications.
• Perform front‑end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR.
• Collaborate closely with physical design and implementation teams to achieve timing closure and PPA goals.
• Apply power-, clock-, and implementation‑aware RTL design practices to minimize silicon risk.

Minimum Qualifications

• Master’s degree in Electrical Engineering with 4+ years of experience, or Bachelor’s degree with 5+ years of pre‑silicon RTL design experience.
• Demonstrated experience developing RTL for complex digital IP from specification through implementation handoff.
• Hands‑on experience with ASIC low‑power design methodologies, including UPF‑based power intent and CDC/RDC analysis.
• Strong knowledge of ASIC design flows, including RTL design, logic synthesis, verification, and static timing analysis.
• Proficiency in Verilog/SystemVerilog and industry‑standard RTL simulation tools.

Preferred Qualifications

• Experience collaborating across architecture, verification, and physical design teams to resolve PPA challenges.
• Knowledge of CDC, RDC, STA, and low‑power techniques in advanced ASIC technology nodes.
• Experience with complex digital logic and/or mixed‑signal‑interfacing RTL development.
• Familiarity with CMOS digital and analog‑integrated circuit concepts and their system‑level impact.
• Previous experience with memory or high‑performance digital design is a strong plus.

Job Profile(s)

Semiconductor Design Engineer 3

Relocation Level: TBD

Equal Employment Opportunity

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.