Senior DRAM Digital Design Engineer — RTL & PPA

Micron Technology, Inc; Boise (ID); On-site; USD 110,000 - 170,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off

Paid holidays

Job summary

Micron Technology, Inc. in Boise, Idaho, seeks a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks.

You will own RTL design, implementation, synthesis, timing analysis, power optimization, and design quality from RTL to GDS. Collaborating with architecture, verification, and physical design teams, you will deliver high-performance, power-efficient designs that meet product specs and PPA goals for next-generation memory products,

Qualifications

• Master's or Bachelor's degree in Electrical Engineering with required years of experience.
• Proven RTL design experience from spec through implementation handoff.
• Experience with front-end design flows including RTL, verification, synthesis, and STA.
• Experience creating and maintaining design constraints (SDC) and multi-mode timing.

Responsibilities

• Design RTL for DRAM digital/mixed-signal blocks aligned with specs and performance targets.
• Perform linting, CDC/RDC analysis, logic synthesis, timing constraints development, and timing closure.
• Collaborate with architecture, verification, and physical design teams to optimize PPA and design quality.
• Develop and maintain synthesis/timing constraints (SDC) and analyze timing reports across scenarios.
• Improve methodologies and automation to speed RTL-to-GDS flow.

Skills

Verilog

SystemVerilog

STA

Synthesis

Timing analysis

Power-aware design

SDC constraints

UPF power intent

Education

Master's degree in Electrical Engineering

Bachelor's degree in Electrical Engineering

Tools

Verilog/SystemVerilog simulators

Job description

Micron Technology, Inc. in Boise, Idaho, seeks a Senior Digital Design Engineer to contribute to the development of advanced DRAM digital and mixed-signal blocks.

You will own RTL design, implementation, synthesis, timing analysis, power optimization, and design quality from RTL to GDS. Collaborating with architecture, verification, and physical design teams, you will deliver high-performance, power-efficient designs that meet product specs and PPA goals for next-generation memory products,