Senior RTL Design Engineer - AI Accelerator

Acceler8 Talent; Mountain View (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Acceler8 Talent is seeking experienced silicon micro-architects and RTL design engineers to build high-performance accelerator silicon across compute, memory management, and high-speed connectivity. You will own design portions from architecture through RTL sign-off and work closely with verification, DFT, physical design, and software teams.

You will contribute to scalable methodologies and drive milestones toward tapeout, while balancing performance, power, and area.

Qualifications

• 4+ years of SystemVerilog RTL experience from architecture specification through production silicon.
• Experience with CPUs/GPUs/AI accelerators or memory-management subsystems is preferred.
• Proficiency in Python, C/C++ and scripting for chip design.

Responsibilities

• Contribute to scalable silicon architecture-to-design methodologies spanning blocks, subsystems, and full-chip development.
• Own entire subsystems, major blocks, or chip-level design deliverables from microarchitecture through sign-off-ready RTL.
• Define and review microarchitecture and design specifications.
• Drive execution toward major silicon milestones including design freeze and tapeout.
• Track and optimize performance, power, area, timing, and design-quality goals.
• Partner closely with verification, DFT, and physical-design engineers throughout the development lifecycle.
• Drive timing and area closure while maintaining functional correctness and design quality.
• Develop production-quality RTL for high-performance compute and accelerator architectures.

Skills

SystemVerilog

RTL design

Python

C/C++

Microarchitecture

Architecture

Synthesis

Lint

Performance optimization

Education

BS/MS in Electrical Engineering

Tools

Verilog

DFT tooling

Job description

Acceler8 Talent is seeking experienced silicon micro-architects and RTL design engineers to build high-performance accelerator silicon across compute, memory management, and high-speed connectivity. You will own design portions from architecture through RTL sign-off and work closely with verification, DFT, physical design, and software teams.

You will contribute to scalable methodologies and drive milestones toward tapeout, while balancing performance, power, and area.