Senior RTL Engineer for AI Accelerators – Lead Design

Oho Group; San Francisco (CA); On-site; USD 270,000 - 360,000; Full time

Job summary

Oho Group is seeking a Senior RTL Design Engineer to drive end-to-end ASIC/SoC design for AI accelerator technology in the Bay Area. You will own critical design work and collaborate with physical design, verification, and leadership teams in a fast-moving startup environment.

The role emphasizes leadership, ownership, and contribution to next-generation accelerator innovation while engaging with top semiconductor partners and industry leaders.

Qualifications

• Experienced in RTL design for ASIC/SoC
• Broad chip design knowledge across subsystems
• Hands-on in fast-moving startup environments
• Familiarity with AI/LLM systems and memory/fabric interconnect is a plus

Responsibilities

• Lead projects end-to-end across the full chip lifecycle
• Collaborate with physical design, verification and leadership teams
• Own design work and drive cross-functional execution
• Help democratise and innovate next-gen accelerator technology

Skills

RTL design

ASIC design

SoC design

high-speed protocols

AI/LLM systems

memory interconnect

Job description

Oho Group is seeking a Senior RTL Design Engineer to drive end-to-end ASIC/SoC design for AI accelerator technology in the Bay Area. You will own critical design work and collaborate with physical design, verification, and leadership teams in a fast-moving startup environment.

The role emphasizes leadership, ownership, and contribution to next-generation accelerator innovation while engaging with top semiconductor partners and industry leaders.