Senior RTL Design Engineer - ASIC/SoC Expert

Wipro; Mountain View (CA); Presencial; USD 80.000 - 160.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical and dental benefits

Disability insurance

Paid time off

Descripción de la vacante

Wipro is seeking a highly experienced ASIC/SoC design engineer in Mountain View, CA. The role emphasizes RTL coding, digital design, and high-throughput/low-latency data transport architectures. Candidates should have 8+ years in ASIC/SoC contexts and strong Verilog/SystemVerilog skills.

Excellent opportunity to work on arbitration fabrics and cutting-edge IP with a broad scope, requiring collaboration across PD and design teams. Competitive compensation and benefits apply.

Formación

• 9+ years of related technical engineering experience.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
• 8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs related to arbitration and fabric logics for high-throughput/low-latency data transport.
• 8+ years expertise in Digital Design including RTL coding in Verilog/System Verilog, RTL2PD tool/flow setup/maintenance/debug: Lint/CDC/RDC/VCLP/Synthesis/Timing constraints/FEV

Responsabilidades

• 9+ years of related technical engineering experience.
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience
• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
• 8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs related to arbitration and fabric logics for high-throughput/low-latency data transport.
• 8+ years expertise in Digital Design including RTL coding in Verilog/System Verilog, RTL2PD tool/flow setup/maintenance/debug: Lint/CDC/RDC/VCLP/Synthesis/Timing constraints/FEV

Conocimientos

RTL coding

Digital Design

Verilog

SystemVerilog

Synthesis

Educación

Bachelor's degree in Electrical Engineering or Computer Engineering or Computer Science

Master's degree in Electrical Engineering, Computer Engineering, or Computer Science

Herramientas

RTL2PD

Descripción del empleo

Wipro is seeking a highly experienced ASIC/SoC design engineer in Mountain View, CA. The role emphasizes RTL coding, digital design, and high-throughput/low-latency data transport architectures. Candidates should have 8+ years in ASIC/SoC contexts and strong Verilog/SystemVerilog skills.

Excellent opportunity to work on arbitration fabrics and cutting-edge IP with a broad scope, requiring collaboration across PD and design teams. Competitive compensation and benefits apply.