RTL Design Engineer

Programmers; United States; Vor Ort; USD 120.000 - 180.000; Vollzeit

Zusammenfassung

Programmers in the United States seeks an experienced ASIC/SoC design engineer to lead RTL design and tape-outs in deep sub-micron technology. You will own Verilog/SystemVerilog design, manage the RTL-to-PD flow, and collaborate with cross-functional teams on high-performance, low-latency data paths.

Applicants should have a track record of successful tape-outs, expertise with AXI interfaces, and a deep understanding of physical design tradeoffs among performance, area, and power.

Qualifikationen

• 9+ years of related engineering experience or equivalent degree combination.
• 8+ years delivering IP/ASIC/SoC designs for arbitration and fabric logics.
• 8+ years Digital Design with RTL coding in Verilog/SystemVerilog; RTL2PD flow experience.

Kenntnisse

Verilog/SystemVerilog RTL coding

RTL2PD flow setup

Lint/CDC/RDC/FEV debugging

Timing constraints

Synthesis

Ausbildung

Bachelor's in EE/CE/CS

Master's in EE/CE/CS

Doctorate in EE/CE/CS

Tools

AXI interfaces

RTL2PD tools

Synthesis tools

Jobbeschreibung

• 9+ years of related technical engineering experience OR bachelor’s degree in electrical engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
• 8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs related to arbitration and fabric logics for high-throughput/low-latency data transport.
• 8+ years expertise in Digital Design including RTL coding in Verilog/System Verilog, RTL2PD tool/flow setup/maintenance/debug: Lint/CDC/RDC/VCLP/Synthesis/Timing constraints/FEV

Additional Or Preferred Qualifications

• 15+ years technical engineering experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience.
• Track record of successful ASIC tape outs in deep sub-micron technologies
• Deep understanding of the physical design impact for each micro-architecture and work closely with PD engineers to find the best tradeoff given the performance/area/power constraints.
• Experienced on a variety of micro-architecture areas such as Complex Control Paths, Memory hierarchies and standard industry interfaces such as Advanced extensible Interface (AXI).
• 5+ years of experience in designing complex control logics on Network-On-Chip ASICs
• Excellent communication skills and ability to facilitate collaboration.