Senior RTL Design Architect for AI Accelerators

Neura Market; Austin, Northern (TX, KY); Hybrid; USD 180,000 - 255,000; Full time

Job summary

SambaNova Systems is seeking a Principal RTL Design Engineer to own microarchitecture and RTL for the RDU, the silicon behind our AI acceleration systems. This senior IC role requires driving from specification through tape-out, managing power, performance and area trade-offs, and shaping timing with aggressive pipeline strategies.

You will write and debug synthesizable SystemVerilog, lead PPA improvements, and collaborate with architecture, verification, and software teams to deliver

Qualifications

• BS degree in a relevant field (EE/CE/CS).
• 7+ years of ASIC RTL design experience.
• Mastery of synthesizable SystemVerilog for high-speed ASICs.
• Experience with power, performance and area trade-offs.
• Leadership in design reviews and mentoring engineers.

Responsibilities

• Own microarchitecture and RTL for major RDU block from spec to tape-out.
• Write, integrate, debug SystemVerilog RTL through full chip flow.
• Own PPA for your area and hit aggressive frequency targets.
• Drive timing closure, lint, CDC, LEC and verification coverage.
• Collaborate with architects, software teams to evaluate features for performance.
• Mentor engineers and contribute to design reviews.

Skills

SystemVerilog

RTL design

Synthesis & STA

Python scripting

Power/Perf/Area optimization

Debugging & Assertions

Microarchitecture knowledge

Design reviews leadership

Education

B.S. in Electrical/Computer Engineering or Computer Science

Tools

SVA

EDA tool suite (unspecified)

Job description

SambaNova Systems is seeking a Principal RTL Design Engineer to own microarchitecture and RTL for the RDU, the silicon behind our AI acceleration systems. This senior IC role requires driving from specification through tape-out, managing power, performance and area trade-offs, and shaping timing with aggressive pipeline strategies.

You will write and debug synthesizable SystemVerilog, lead PPA improvements, and collaborate with architecture, verification, and software teams to deliver