Senior Principal SI/PI Engineer — High-Speed IP Debug

Cadence Design Systems; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Job summary

Cadence Design Systems is seeking a Sr Principal SI/PI Engineer to join the HPP IP R&D Group. This hands-on role focuses on high-speed IP products, SI/PI optimization, and collaboration with chip designers.

You will work on test chip package design, evaluation board optimization, and provide channel models. Requires MS/PhD in EE, 3+ years SerDes/PHY experience, and proficiency with Sigrity/HFSS/SIwave; IBIS-AMI simulations; lab instrumentation.

Qualifications

• MS or PhD in Electrical Engineering (or similar degree).
• 3+ years of experience preferably working with high speed SerDes and PHYs.
• Good understanding of high speed SerDes architecture.
• Hands on lab experience with high speed test equipment (oscilloscopes, TDRs, VNAs, spectrum analyzers).
• Fluent with using 3D and 2.5D extraction tools like Sigrity Clarity/PowerSI or Ansys HFSS/SIwave.
• Experience with IBIS-AMI model simulations.
• Experience with simulation results to lab measurement correlation.
• Good understanding of PCB/FCBGA design rules and requirements.
• Strong debugging and problem-solving skills.
• Excellent communication and presentation skills to stakeholders.

Responsibilities

• Work on test chip package design SI/PI optimization and verification.
• Work on evaluation board design optimization for best SI/PI performance.
• Provide extracted and measured channel models for chip designers in the R&D team.
• Help with package and PCB SI/PI design guidelines and customer support on SI/PI inquiries.
• Review customer package and board designs and simulations; provide feedback to ensure best IP performance.
• Work on link performance simulations using S-parameter channel models and IBIS-AMI models.
• Help with SI/PI related debug of test chips or customer ASICs in the lab.

Skills

High-speed SerDes

Lab debugging

Communication

Problem solving

PCB/FCBGA design rules

Education

MS or PhD in Electrical Engineering

Tools

Sigrity Clarity/PowerSI

Ansys HFSS/SIwave

IBIS-AMI simulations

Job description

Cadence Design Systems is seeking a Sr Principal SI/PI Engineer to join the HPP IP R&D Group. This hands-on role focuses on high-speed IP products, SI/PI optimization, and collaboration with chip designers.

You will work on test chip package design, evaluation board optimization, and provide channel models. Requires MS/PhD in EE, 3+ years SerDes/PHY experience, and proficiency with Sigrity/HFSS/SIwave; IBIS-AMI simulations; lab instrumentation.