Senior Principal Memory Controller RTL Lead (Hybrid)

Rambus.com; Hillsboro (OR); Hybrid; USD 146,000 - 271,000; Full time

Job summary

Rambus seeks a Senior Logic Design Engineer to join the Memory Controller team in Hillsboro, OR. Lead RTL design, microarchitecture, and IP integration for high-performance memory controllers, collaborating across architecture, verification, and customer teams.

The role combines leadership with hands-on design, debugging, and delivery of production-quality silicon IP, with a hybrid work model enabling three onsite days per week and two remote days.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• Typically 8+ years of RTL design, IP development, SoC integration, or related semiconductor design roles.
• Expert-level proficiency with Verilog/SystemVerilog and understanding of digital design, microarchitecture, timing, and low-power design concepts.
• Hands-on experience delivering production-quality IP or silicon products across the development lifecycle.
• Strong debugging skills across RTL simulation, verification environments, integration flows, and customer use cases.
• Experience with memory controllers, high-performance interfaces, data center architectures, or configurable silicon IP preferred.
• Demonstrated ability to lead technical discussions, mentor engineers, and communicate effectively across teams.

Responsibilities

• Define microarchitecture, develop high-quality RTL, and guide implementation tradeoffs across performance, area, power, timing, and configurability.
• Lead the design, integration, validation, and delivery of complex Memory Controller IP features and releases.
• Drive integration of internal and 3rd party IP, including interface definition, configuration, documentation, and quality closure.
• Lead debug of complex simulation, integration, and customer-reported issues through root cause and corrective action.
• Collaborate with verification teams to develop robust test plans, improve coverage, and ensure design intent is fully validated.
• Provide technical guidance and mentoring to engineers while promoting best practices in RTL design, review, documentation, and methodology.
• Partner with customers and field teams to support integration, resolve technical issues, and influence product improvements.

Skills

Verilog/SystemVerilog

RTL design

Microarchitecture

Timing analysis

Low-power design

Debugging RTL

Memory controller IP

High-performance interfaces

Data center architectures

Leadership & mentoring

Cross-team communication

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Master’s degree preferred

Job description

Rambus seeks a Senior Logic Design Engineer to join the Memory Controller team in Hillsboro, OR. Lead RTL design, microarchitecture, and IP integration for high-performance memory controllers, collaborating across architecture, verification, and customer teams.

The role combines leadership with hands-on design, debugging, and delivery of production-quality silicon IP, with a hybrid work model enabling three onsite days per week and two remote days.