Senior Memory Controller RTL Architect (Hybrid)

Socket.dev; Hillsboro (OR); Hybrid; USD 146,000 - 271,000; Full time

Job summary

Rambus in Hillsboro, OR is seeking a Senior Logic Design Engineer to join the Memory Controller team. You will design RTL, define microarchitecture, and guide complex IP features from concept to deployment.

The role emphasizes collaboration with architecture, verification, and customer-facing teams; hybrid work with onsite 3 days/week and 2 days remote; requires strong Verilog/SystemVerilog and 8+ years of RTL/IP experience.

Qualifications

• 8+ years of RTL design or IP development experience.
• Expert-level Verilog/SystemVerilog knowledge with digital design expertise.
• Experience delivering production IP or silicon across lifecycle.
• Strong debugging across RTL simulation and verification environments.
• Experience with memory controllers or high-performance interfaces is a plus.

Responsibilities

• Define microarchitecture, develop RTL, and balance performance, area, power, timing, and configurability.
• Lead design, integration, validation, and delivery of Memory Controller IP features.
• Drive IP integration with internal and 3rd party components, including docs and quality closure.
• Lead debugging of simulation, integration, and customer-reported issues.
• Collaborate with verification to improve test coverage and validate design intent.
• Mentor engineers and promote RTL design best practices; support customers and field teams.

Skills

Verilog/SystemVerilog

RTL design

Debugging

Memory controllers

Collaboration

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree preferred

Job description

Rambus in Hillsboro, OR is seeking a Senior Logic Design Engineer to join the Memory Controller team. You will design RTL, define microarchitecture, and guide complex IP features from concept to deployment.

The role emphasizes collaboration with architecture, verification, and customer-facing teams; hybrid work with onsite 3 days/week and 2 days remote; requires strong Verilog/SystemVerilog and 8+ years of RTL/IP experience.