Senior Logic Design Engineer - Memory Controller (Hybrid)

Rambus.com; Hillsboro (OR); Hybrid; USD 98,000 - 181,000; Full time

Benefits offered by this job

Equity

Bonus

401(k) matching

Medical benefits

Gym membership

Job summary

Rambus, a premier chip and silicon IP provider, seeks a Senior Logic Design Engineer for our Memory Controller team in Hillsboro, OR. You will define microarchitecture, develop RTL, and guide complex IP features from concept to customer deployment.

Lead design collaborations across architecture, verification, and product teams in a hybrid work model, three days onsite and two days remote. 8+ years of RTL experience and Verilog expertise are expected.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 8+ years of RTL design, IP development, or SoC integration experience.
• Expert-level Verilog/SystemVerilog with strong digital design, timing, and low-power concepts.

Responsibilities

• Define microarchitecture, develop RTL, and guide tradeoffs across performance, area, power, timing, and configurability.
• Lead the design, integration, validation, and delivery of Memory Controller IP features and releases.
• Drive integration of internal and 3rd party IP, including interface definition, configuration, documentation, and quality closure.
• Lead debugging of complex simulation, integration, and customer-reported issues through root cause analysis.
• Collaborate with verification teams to develop robust test plans, improve coverage, and ensure design intent is validated.
• Provide technical guidance and mentoring to engineers while promoting best practices in RTL design and methodology.
• Partner with customers and field teams to support integration and influence product improvements.

Skills

RTL design

Verilog/SystemVerilog

Debugging

Leadership

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree preferred

Job description

Rambus, a premier chip and silicon IP provider, seeks a Senior Logic Design Engineer for our Memory Controller team in Hillsboro, OR. You will define microarchitecture, develop RTL, and guide complex IP features from concept to customer deployment.

Lead design collaborations across architecture, verification, and product teams in a hybrid work model, three days onsite and two days remote. 8+ years of RTL experience and Verilog expertise are expected.