Senior RTL Design Engineer, Memory Controller

Socket.dev; Hillsboro (OR); Hybrid; USD 98,000 - 181,000; Full time

Job summary

Rambus in Hillsboro, OR is seeking a Senior Logic Design Engineer to join the Memory Controller team. In this full-time role you will define microarchitecture, develop RTL, and deliver complex IP features while coordinating with architecture, verification, and customer teams.

You should have a Bachelor’s in EE/CE (Master’s preferred) and 8+ years in RTL design or IP development, with expert SystemVerilog/Verilog and strong debugging skills.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• Typically 8+ years of experience in RTL design, IP development, SoC integration, or related semiconductor design roles.
• Expert-level proficiency with Verilog/SystemVerilog and strong understanding of digital design, microarchitecture, timing, and low-power design concepts.
• Hands-on experience delivering production-quality IP or silicon products through multiple phases of the development lifecycle.
• Strong debugging skills across RTL simulation, verification environments, integration flows, and customer use cases.
• Experience with memory controllers, high-performance interfaces, data center architectures, or configurable silicon IP preferred.
• Demonstrated ability to lead technical discussions, make sound engineering tradeoffs, mentor engineers, and communicate effectively across teams and with customers.

Responsibilities

• Define microarchitecture, develop high-quality RTL, and guide implementation tradeoffs across performance, area, power, timing, and configurability.
• Lead the design, integration, validation, and delivery of complex Memory Controller IP features and releases.
• Drive integration of internal and 3rd party IP, including interface definition, configuration, documentation, and quality closure.
• Lead debug of complex simulation, integration, and customer-reported issues through root cause and corrective action.
• Collaborate with verification teams to develop robust test plans, improve coverage, and ensure design intent is fully validated.
• Provide technical guidance and mentoring to engineers while promoting best practices in RTL design, review, documentation, and methodology.
• Partner with customers and field teams to support integration, resolve technical issues, and influence product improvements.

Skills

Leadership & mentoring

Verilog/SystemVerilog

Debugging

Communication with customers

RTL design

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree preferred

Job description

Rambus in Hillsboro, OR is seeking a Senior Logic Design Engineer to join the Memory Controller team. In this full-time role you will define microarchitecture, develop RTL, and deliver complex IP features while coordinating with architecture, verification, and customer teams.

You should have a Bachelor’s in EE/CE (Master’s preferred) and 8+ years in RTL design or IP development, with expert SystemVerilog/Verilog and strong debugging skills.