Senior Logic Design Engineer - Hybrid Memory Controller

Rambus; Hillsboro (OR); Hybrid; USD 98,000 - 181,000; Full time

Benefits offered by this job

Hybrid work environment

Job summary

Rambus, a premier chip and silicon IP provider, seeks a Senior Logic Design Engineer for the Memory Controller team in Hillsboro, OR. In this full-time role, you will define microarchitecture, develop RTL, and lead IP features from concept to deployment while mentoring engineers and coordinating with cross-functional teams.

You will work in a hybrid environment with on-site and remote days, collaborating with architecture, verification, and product teams to deliver high-quality silicon IP

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• Typically 8+ years of RTL design, IP development, SoC integration, or related roles.
• Expert-level proficiency with Verilog/SystemVerilog and strong digital design knowledge.
• Experience leading technical discussions, mentoring engineers, and cross-team collaboration.

Responsibilities

• Define microarchitecture, develop high-quality RTL, and guide tradeoffs across perf, area, power, timing.
• Lead the design, integration, validation, and delivery of Memory Controller IP features.
• Drive integration of internal and 3rd party IP, including interface definition and docs.
• Lead debug of complex simulations, integration, and customer issues to root cause.
• Collaborate with verification to improve coverage and validate design intent.
• Mentor engineers and promote RTL design best practices and documentation.
• Partner with customers and field teams to support integration and product improvements.

Skills

RTL design

Verilog/SystemVerilog

Debugging

Team leadership

Communication

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s degree preferred

Job description

Rambus, a premier chip and silicon IP provider, seeks a Senior Logic Design Engineer for the Memory Controller team in Hillsboro, OR. In this full-time role, you will define microarchitecture, develop RTL, and lead IP features from concept to deployment while mentoring engineers and coordinating with cross-functional teams.

You will work in a hybrid environment with on-site and remote days, collaborating with architecture, verification, and product teams to deliver high-quality silicon IP