Senior/Principal Layout Engineer – High-Speed Memory SI/PI

Micron Technology, Inc.; California (MO); On-site; USD 202,000 - 344,000; Full time

Job summary

Micron Technology seeks a Senior/Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors. You will lead layout-driven exploration, collaborate with SI/PI teams, and influence design decisions with layout insights.

Ideal candidates have 8+ years in high-speed PCB layout, deep DDR/LPDDR experience, and proficiency with Cadence Allegro/OrCAD; a BS in EE is required.

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 8-15+ years of experience in high-speed PCB layout with strong ownership of complex designs.
• Deep expertise in: DDR/LPDDR memory interfaces or similar ultra-high-speed parallel interfaces.
• Signal integrity and power integrity understanding (transmission lines, loss, decoupling).
• Proficient in Cadence Allegro / OrCAD or equivalent high-end layout tools.

Responsibilities

• Lead layout-driven architecture exploration for next-generation memory modules and interconnects.
• Evaluate form factor, routing topology, and pinout tradeoffs to enable future bandwidth and density targets.
• Define feasible design envelopes (routing complexity, layer count, escape feasibility, via strategy).
• Collaborate with SI/PI teams to co-optimize channel topology, losses, reflections, and crosstalk mitigation.
• Mentor junior engineers and shape layout best practices across the organization.

Skills

High-speed PCB layout

SI/PI co-design

DDR/LPDDR memory interfaces

Cadence Allegro / OrCAD

AI tools in daily job

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Allegro / OrCAD

Job description

Micron Technology seeks a Senior/Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors. You will lead layout-driven exploration, collaborate with SI/PI teams, and influence design decisions with layout insights.

Ideal candidates have 8+ years in high-speed PCB layout, deep DDR/LPDDR experience, and proficiency with Cadence Allegro/OrCAD; a BS in EE is required.