Senior/Principal Layout Engineer: High-Speed PCB Architect

Micron Technology; San Jose (CA); On-site; USD 202,000 - 344,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology is seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors. The role requires deep expertise in high-speed layout, SI/PI co-design, and advanced PCB technologies, with the ability to influence architecture through layout-driven modeling.

US base salary range is $202,000.00 - $344,000.00 a year. Ideal candidates will mentor junior engineers and collaborate with cross-functional teams to

Qualifications

• 8-15+ years of high-speed PCB layout experience.
• Deep expertise in DDR/LPDDR memory interfaces and SI/PI.
• Ability to influence architecture through layout constraints.
• Experience working in cross-functional architecture or pathfinding environments.
• Proficient in using AI tools in daily job.

Responsibilities

• Lead layout-driven architecture exploration for next-generation memory modules and interconnects.
• Evaluate form factor, routing topology, and pinout tradeoffs to enable future bandwidth and density targets.
• Define feasible design envelopes (routing complexity, layer count, escape feasibility, via strategy).
• Collaborate with SI/PI teams to co-optimize: channel topology, loss, reflection, crosstalk mitigation, return path integrity.
• Define and influence SI/PI budgets at the module level.
• Drive adoption of next-generation PCB technologies, including ultra-low-loss materials, HDI, hybrid bonding.
• Help develop layout methodologies and constraints for >10-20+ Gb/s signaling.
• Establish design rules bridging architecture - SI/PI - layout - manufacturing.
• Drive design reviews, risk assessments, and trade-off analysis.
• Mentor junior engineers and shape layout best practices across the organization.

Skills

DDR/LPDDR memory interfaces

Signal integrity

Power integrity

AI tools

Education

Bachelor’s degree in Electrical Engineering

Tools

Cadence Allegro / OrCAD

Job description

Micron Technology is seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors. The role requires deep expertise in high-speed layout, SI/PI co-design, and advanced PCB technologies, with the ability to influence architecture through layout-driven modeling.

US base salary range is $202,000.00 - $344,000.00 a year. Ideal candidates will mentor junior engineers and collaborate with cross-functional teams to