Senior / Principal Layout Engineer – Module Architecture (Pathfinding)

Micron; San Jose (CA); On-site; USD 202,000 - 344,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off + holidays

Equity and bonuses

Job summary

Micron Technology is seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors. This role sits in the Module Architecture Group, using layout-driven insights to influence design decisions.

You will lead layout-driven exploration, evaluate routing topologies, define design envelopes for extreme-speed signaling, and mentor junior engineers while collaborating with SI/PI teams.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 8–15+ years of experience in high-speed PCB layout.
• Deep expertise in DDR/LPDDR memory interfaces or similar ultra-high-speed interfaces.
• Proficient with Cadence Allegro/OrCAD.

Responsibilities

• Lead layout-driven architecture exploration for next-generation memory modules.
• Evaluate form factor, routing topology, and pinout tradeoffs.
• Define feasible design envelopes (routing complexity, layer count, via strategy).
• Mentor junior engineers and influence layout best practices.

Skills

High-speed layout

SI/PI co-design

Advanced PCB tech

AI tools

Education

Bachelor’s degree in Electrical Engineering

Tools

Cadence Allegro/OrCAD

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

We are seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors (DDR6, LPDDR6/LPDDR7, MRDIMM Gen3/Gen4, SOCAMM2 and beyond). This role operates within the Module Architecture Group, focusing on pre-product definition, feasibility studies, and design tradeoff exploration. The ideal candidate brings deep expertise in high-speed layout, SI/PI co-design, and advanced PCB technologies, with the ability to influence architecture decisions through layout-driven insights and modeling-informed design.

Essential Duties and Responsibilities

• Lead layout-driven architecture exploration for next-generation memory modules and interconnects
• Evaluate form factor, routing topology, and pinout tradeoffs to enable future bandwidth and density targets
• Define feasible design envelopes (routing complexity, layer count, escape feasibility, via strategy)
• Collaborate closely with SI/PI teams to co-optimize: Channel topology (fly-by, point-to-point, multi-drop evolution)
• Loss, reflection, and crosstalk mitigation strategies
• Return path integrity and reference plane design
• Define and influence SI/PI budgets at the module level
• Drive adoption of next-generation PCB technologies, including: Ultra-low-loss materials Advanced HDI (microvias, stacked vias, via-in-pad) Hybrid bonding / advanced packaging integration (where applicable)
• Help develop next-gen layout methodologies and constraints for >10–20+ Gb/s signaling
• Help define: Routing rules for extreme speed interfaces
• Skew/jitter budgets translated into physical constraints
• Reference design guidelines for future programs
• Establish design rules that bridge architecture > SI/PI > layout > manufacturing
• Drive design reviews, risk assessments, and trade-off analysis
• Influence JEDEC and industry standards through practical layout feasibility input
• Mentor junior engineers and shape layout best practices across the organization

Education/Experience requirements

• Bachelor’s degree in Electrical Engineering or related field
• 8–15+ years of experience in high-speed PCB layout, with strong ownership of complex designs
• Deep expertise in: DDR/LPDDR memory interfaces or similar ultra-high-speed parallel interfaces
• Signal integrity (transmission lines, discontinuities, channel loss mechanisms)
• Power integrity (PDN design, target impedance, decoupling optimization)
• Advanced proficiency with: Cadence Allegro / OrCAD (or equivalent high-end layout tools)
• Proven ability to influence architecture decisions through physical design constraints
• Experience working in cross-functional architecture or pathfinding environments
• Proficient in using AI tools in daily job

The US base salary range that Micron Technology estimates it could pay for this full-time position is: $202,000.00 - $344,000.00 a year. Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs.

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.