Senior Layout Engineer

Infobahn Softworld Inc; Santa Clara (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Infobahn Softworld Inc. is seeking an experienced Lead Custom Memory Layout Engineer to drive end-to-end physical design for high-performance SRAM bitcell arrays, memory periphery, and full memory macros.

You will work on cutting-edge CMOS nodes (FinFET / GAA, 5nm/3nm and below) with CAD, PnR, and foundry teams to deliver tapeout-ready memory IPs. The role requires strong leadership in layout, verification, and sign-off, plus mentorship of junior engineers.

Qualifications

• 10+ years of custom IC layout experience, with at least 5+ years dedicated to SRAM, memory compilers, or full-custom memory IP layout.
• Proven track record on advanced CMOS processes (FinFET / GAA at 5nm, 3nm, or smaller nodes).
• Expert-level command of Cadence Virtuoso layout suite and Calibre / ICV verification engines.
• Familiarity with SKILL scripting, layout automation, or modern layout AI utilities is a strong plus.

Responsibilities

• Full Macro Execution: Own the full-custom layout cycle for SRAM bitcell arrays, control logic, I/O, periphery, test chips, and complete memory macro assembly.
• Floorplanning & Power Grid: Architect optimized floorplans, power/ground meshes, pin access, boundary cells, and routing channels to minimize parasitic effects and silicon area.
• Physical Verification: Lead rule execution, debugging, and clean-up across DRC, LVS, ERC, Antenna, and DFM using Siemens Calibre, Synopsys ICV, or equivalent EDA flows.
• Reliability & Sign-Off: Mitigate Layout-Dependent Effects (LDE/LOD), ensure tight device matching/symmetry, perform dummy fill, and drive EM/IR drop analysis to achieve sign-off closure.
• Cross-Functional Collaboration: Partner with Circuit Designers, CAD, and PnR/SOC integration teams to guarantee seamless macro drop-in and resolve top-level interface constraints.
• Mentorship & Methodology: Establish layout standards, sign-off checklists, and mentor junior engineers on advanced-node best practices.

Skills

Custom IC layout

SRAM / memory IP layout

Layout automation / SKILL scripting

Education

BSEE

MSEE

Tools

Cadence Virtuoso

Calibre / ICV

Job description

Job Title: Principal / Senior Staff Memory Layout Engineer

Experience Level: 10+ Years

12+ Months Contract

About the Role:

We are seeking an experienced Lead Custom Memory Layout Engineer to drive end-to-end physical design for high-performance SRAM bitcell arrays, memory periphery, and full memory macros. In this role, you will work on cutting-edge advanced CMOS nodes (FinFET / GAA, 5nm/3nm and below), partnering closely with circuit design, CAD, PnR, and foundry teams to deliver tapeout-ready memory IPs.

Key Responsibilities:

• Full Macro Execution: Own the full-custom layout cycle for SRAM bitcell arrays, control logic, I/O, periphery, test chips, and complete memory macro assembly.
• Floorplanning & Power Grid: Architect optimized floorplans, power/ground meshes, pin access, boundary cells, and routing channels to minimize parasitic effects and silicon area.
• Physical Verification: Lead rule execution, debugging, and clean-up across DRC, LVS, ERC, Antenna, and DFM using Siemens Calibre, Synopsys ICV, or equivalent EDA flows.
• Reliability & Sign-Off: Mitigate Layout-Dependent Effects (LDE/LOD), ensure tight device matching/symmetry, perform dummy fill, and drive EM/IR drop analysis to achieve sign-off closure.
• Cross-Functional Collaboration: Partner with Circuit Designers, CAD, and PnR/SOC integration teams to guarantee seamless macro drop-in and resolve top-level interface constraints.
• Mentorship & Methodology: Establish layout standards, sign-off checklists, and mentor junior engineers on advanced-node best practices.

Qualifications:

• BSEE, MSEE, or equivalent practical industry experience.
• 10+ years of custom IC layout experience, with at least 5+ years dedicated to SRAM, memory compilers, or full-custom memory IP layout.
• Proven track record on advanced CMOS processes (FinFET / GAA at 5nm, 3nm, or smaller nodes).
• Expert-level command of Cadence Virtuoso layout suite and Calibre / ICV verification engines.
• Deep understanding of deep-submicron effects: electromigration, IR drop, DFM, density/fill rules, and parasitic extraction.
• Familiarity with SKILL scripting, layout automation, or modern layout AI utilities is a strong plus.