Senior Principal Pathfinding Layout Architect – Memory

Micron; San Jose (CA); On-site; USD 202,000 - 344,000; Full time

Benefits offered by this job

Medical, dental, vision plans

Paid time off + holidays

Equity and bonuses

Job summary

Micron Technology is seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors. This role sits in the Module Architecture Group, using layout-driven insights to influence design decisions.

You will lead layout-driven exploration, evaluate routing topologies, define design envelopes for extreme-speed signaling, and mentor junior engineers while collaborating with SI/PI teams.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 8–15+ years of experience in high-speed PCB layout.
• Deep expertise in DDR/LPDDR memory interfaces or similar ultra-high-speed interfaces.
• Proficient with Cadence Allegro/OrCAD.

Responsibilities

• Lead layout-driven architecture exploration for next-generation memory modules.
• Evaluate form factor, routing topology, and pinout tradeoffs.
• Define feasible design envelopes (routing complexity, layer count, via strategy).
• Mentor junior engineers and influence layout best practices.

Skills

High-speed layout

SI/PI co-design

Advanced PCB tech

AI tools

Education

Bachelor’s degree in Electrical Engineering

Tools

Cadence Allegro/OrCAD

Job description

Micron Technology is seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors. This role sits in the Module Architecture Group, using layout-driven insights to influence design decisions.

You will lead layout-driven exploration, evaluate routing topologies, define design envelopes for extreme-speed signaling, and mentor junior engineers while collaborating with SI/PI teams.