Senior/Principal Layout Engineer - Pathfinding Architecture

Micron Technology, Inc; San Jose (CA); On-site; USD 202,000 - 344,000; Full time

Job summary

Micron Technology, Inc. in San Jose is seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors.

The role focuses on pre-product definition, feasibility studies, and design tradeoff exploration within the Module Architecture Group. You will lead layout-driven architecture exploration, evaluate routing/topology tradeoffs, define design envelopes, and collaborate with SI/PI teams to push bandwidth, density,

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 8–15+ years of experience in high-speed PCB layout.
• Deep expertise in: DDR/LPDDR memory interfaces or similar ultra-high-speed parallel interfaces.
• Signal integrity (transmission lines, discontinuities, channel loss mechanisms).
• Power integrity (PDN design, target impedance, decoupling optimization).
• Advanced proficiency with: Cadence Allegro / OrCAD (or equivalent high-end layout tools).
• Proven ability to influence architecture decisions through physical design constraints.
• Experience working in cross-functional architecture or pathfinding environments.
• Proficient in using AI tools in daily job.

Responsibilities

• Lead layout-driven architecture exploration for next-generation memory modules and interconnects.
• Evaluate form factor, routing topology, and pinout tradeoffs to enable future bandwidth and density targets.
• Define feasible design envelopes (routing complexity, layer count, escape feasibility, via strategy).
• Collaborate closely with SI/PI teams to co-optimize channel topology, loss, reflection, and crosstalk mitigation strategies; return path integrity and reference plane design.
• Define and influence SI/PI budgets at the module level.
• Drive adoption of next-generation PCB technologies, including ultra-low-loss materials, advanced HDI, and hybrid bonding/advanced packaging.
• Help develop next-gen layout methodologies and constraints for >10–20+ Gb/s signaling.
• Help define routing rules, skew/jitter budgets, and reference design guidelines for future programs.
• Establish design rules bridging architecture → SI/PI → layout → manufacturing; drive design reviews and risk assessments.
• Influence JEDEC and industry standards through practical layout feasibility input.
• Mentor junior engineers and shape layout best practices across the organization.

Skills

High-speed PCB layout

DDR/LPDDR memory interfaces

Signal integrity

Power integrity

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Allegro/OrCAD

Job description

Micron Technology, Inc. in San Jose is seeking a Senior / Principal Layout Engineer to drive pathfinding and architecture exploration for next-generation memory modules and form factors.

The role focuses on pre-product definition, feasibility studies, and design tradeoff exploration within the Module Architecture Group. You will lead layout-driven architecture exploration, evaluate routing/topology tradeoffs, define design envelopes, and collaborate with SI/PI teams to push bandwidth, density,