Senior Principal DFT Architect — End-to-End IC Strategy

SiMa.ai, Inc.; San Jose (CA); On-site; USD 231,000 - 358,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

SiMa.ai, Inc. in San Jose, CA seeks a Sr. Principal DFT Engineer to own the DFT architecture for next-generation industrial, robotic, and automotive ICs. You will define the strategy and drive its hands-on execution from RTL to tape-out, partnering with RTL, verification, and physical design teams to ensure silicon correctness.

You will mentor the DFT team, remove blockers, and raise the technical bar across all DFT activities while delivering robust, scalable solutions on advanced finFET nodes.

Qualifications

• BSEE with 18+ years of experience in DFT.
• MSEE or PhD with 16+ years in hardware design and DFT.
• End-to-end DFT execution from architecture to tape-out.
• Proficient in Verilog and SystemVerilog.
• Hands-on with EDA tools such as Synopsys SMS/Testmax and Mentor Tessent.

Responsibilities

• Set the DFT architecture and methodology strategy for SiMa's upcoming ICs.
• Drive execution of that strategy across RTL design, verification, and physical design to ensure silicon holds up in silicon.
• Be the technical anchor for the broader DFT team, enabling their success day to day.
• Oversee architecture through tape-out through pattern bring-up on advanced finFET nodes.
• Collaborate with cross-functional and cross-site teams to implement DFT strategies.

Skills

VLSI design

Verilog

SystemVerilog

DFT expertise

End-to-end DFT execution

Education

BSEE

MSEE/PhD

Tools

Synopsys SMS/Testmax

Mentor Tessent

VCS/Verdi

Fusion Compiler

PrimeTime

PrimePower

RedHawk

StarRC

Job description

SiMa.ai, Inc. in San Jose, CA seeks a Sr. Principal DFT Engineer to own the DFT architecture for next-generation industrial, robotic, and automotive ICs. You will define the strategy and drive its hands-on execution from RTL to tape-out, partnering with RTL, verification, and physical design teams to ensure silicon correctness.

You will mentor the DFT team, remove blockers, and raise the technical bar across all DFT activities while delivering robust, scalable solutions on advanced finFET nodes.