AI-Driven DFT Engineer for Next-Gen SoCs

Ricursive; Palo Alto (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Ricursive Intelligence is seeking a Senior DFT Engineer to own end-to-end DFT for complex SoCs at advanced nodes. You will design architecture, plan MBIST/BISR, and sign off ATPG, partnering with RTL, DV, and PD teams to ship silicon.

You will lead post-silicon bring-up with foundry/OSAT partners, define coverage strategies, and push AI-native enhancements to DFT workflows, ensuring quality, performance, and yield.

Qualifications

• BS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 5+ years hands-on DFT experience owning full lifecycle on complex SoCs/IPs: DFT architecture and specification, scan/compression insertion, MBIST/BISR, boundary scan and IJTAG, test-mode timing, DFT verification and DRC closure, fault-model/coverage analysis, ATPG pattern generation and signoff.
• Day-one fluency in at least one production DFT stack and gate-level simulation, with Tcl and Python scripting and Verilog/SystemVerilog for test logic and testbenches.
• Post-silicon experience bringing up ATPG/MBIST on ATE, debugging CP/FT/SLT, and working with foundry/OSAT.
• Practical use of AI coding/tools in DFT flow and where they help or not.

Responsibilities

• Own DFT architecture and insertion for complex silicon at advanced nodes, including hierarchical scan, compression, BIST, MBIST, BISR, boundary scan and IJTAG integration with RTL/PD/STA flow.
• Define fault-model and coverage strategy and own ATPG generation, fault simulation, coverage closure, pattern verification, and DFT signoff to tapeout.
• Drive post-silicon test from first silicon to production with ATE pattern conversion, CP, FT, SLT, and yield improvement with foundry/OSAT partners.
• Integrate DFT with RTL, DV, and PD: set DFT requirements early, verify test logic with functional verification, close test-mode timing with PD/STA.
• Make DFT AI-native: influence AI planning and debugging of DFT, measure via coverage and DPPM.
• Partner cross-functionally on chip design infrastructure and automation, encoding DFT knowledge into reusable flows and evaluation targets.

Skills

DFT architecture

MBIST

ATPG signoff

IJTAG

Verilog/SystemVerilog

Python scripting

Tcl scripting

post-silicon bring-up

Education

BS in Electrical Engineering or related

Tools

Synthesis tools

Gate-level simulators

Job description

Ricursive Intelligence is seeking a Senior DFT Engineer to own end-to-end DFT for complex SoCs at advanced nodes. You will design architecture, plan MBIST/BISR, and sign off ATPG, partnering with RTL, DV, and PD teams to ship silicon.

You will lead post-silicon bring-up with foundry/OSAT partners, define coverage strategies, and push AI-native enhancements to DFT workflows, ensuring quality, performance, and yield.