Sr. Principal DFT Engineer (AI2533)

SiMa.ai, Inc.; San Jose (CA); Sur place; USD 231 000 - 358 000; Plein temps

Avantages offerts par ce poste

Equity

Benefits package

Résumé du poste

SiMa.ai, Inc. in San Jose, CA seeks a Sr. Principal DFT Engineer to own the DFT architecture for next-generation industrial, robotic, and automotive ICs. You will define the strategy and drive its hands-on execution from RTL to tape-out, partnering with RTL, verification, and physical design teams to ensure silicon correctness.

You will mentor the DFT team, remove blockers, and raise the technical bar across all DFT activities while delivering robust, scalable solutions on advanced finFET nodes.

Qualifications

• BSEE with 18+ years of experience in DFT.
• MSEE or PhD with 16+ years in hardware design and DFT.
• End-to-end DFT execution from architecture to tape-out.
• Proficient in Verilog and SystemVerilog.
• Hands-on with EDA tools such as Synopsys SMS/Testmax and Mentor Tessent.

Responsabilités

• Set the DFT architecture and methodology strategy for SiMa's upcoming ICs.
• Drive execution of that strategy across RTL design, verification, and physical design to ensure silicon holds up in silicon.
• Be the technical anchor for the broader DFT team, enabling their success day to day.
• Oversee architecture through tape-out through pattern bring-up on advanced finFET nodes.
• Collaborate with cross-functional and cross-site teams to implement DFT strategies.

Connaissances

VLSI design

Verilog

SystemVerilog

DFT expertise

End-to-end DFT execution

Formation

BSEE

MSEE/PhD

Outils

Synopsys SMS/Testmax

Mentor Tessent

VCS/Verdi

Fusion Compiler

PrimeTime

PrimePower

RedHawk

StarRC

Description du poste

About SiMa.ai:

SiMa.ai™ is scaling Physical AI in Robotics, Automotive, Industrial, Aerospace and Defense, and Medical markets. We have created the industry's best purpose-built, software centric Physical AI HW/SW platform that leads the industry in Ease of use, performance, and power efficiency. SiMa.ai is led by technologists and business veterans backed by a set of top investors committed to helping customers bring ML on their platforms. SiMa.ai was founded in 2018, has raised $355M and is backed by Fidelity Management & Research Company, Maverick Capital, Point72, MSD Partners, VentureTech Alliance and more. For more information, visit https://sima.ai/.

We're looking for a Sr. Principal-level DFT leader to own that foundation. This isn't a role focused on executing someone else's test plan — you'll be the person defining how SiMa approaches Design for Test at the architecture level, then staying hands-on through execution, tape-out, and pattern bring-up across our next generation of SoCs.

What you'll do

You'll set the DFT architecture and methodology strategy for SiMa's upcoming industrial, robotic, and automotive ICs — decisions that ripple through every downstream team touching the chip. From there, you'll drive execution of that strategy directly, working shoulder-to-shoulder with RTL design, verification, and physical design teams to make sure the architecture you've defined actually holds up in silicon. You'll also be a technical anchor for the broader DFT team — not managing them on paper, but enabling their success day to day, unblocking hard problems, and raising the technical bar across the group.

This is a role for someone who wants ownership of the whole DFT lifecycle, not one slice of it — architecture through tape-out through pattern bring-up, on advanced finFET nodes, across multiple ICs.

Job Title:Sr. Principal DFT Engineer

Job Location: San Jose, CA (This position requires a full-time, on-site presence in our San Jose, CA office)

Job ID: AI2533

Key Responsibilities:

• Technical leadership across various DFT endeavors at SiMa.
• DFT architecture and methodology development for latest industrial, robotic, and automotive ICs.
• Responsible for the execution of above DFT architecture/methodology in future SiMa SoC(s).
• Work closely with other members of DFT team to enable their success.
• Work across all H/W functions (RTL design, verification, and physical design) towards the successful implementation of above DFT strategies.

Required Background:

• BSEE with 18+ years of experience or MSEE/PhD with 16+ years of experience
• Commanding knowledge of all aspects of DFT
• Experience with end-to-end DFT execution from architecture to tape-out to pattern bringup across multiple ICs in advanced finFET technology.
• In-depth knowledge of VLSI design as well as hardware description languages such as Verilog and System Verilog.
• Deep hands‑on experience with latest EDA tools like Synopsys SMS/Testmax or Mentor Tessent.
• Good working knowledge of non‑DFT EDA tools like VCS/Verdi, Fusion Compiler, PrimeTime, PrimePower, RedHawk, StarRC, etc. is preferred plus.
• Strong problem solving and debug capabilities is must.
• Should be proficient at working with cross functional and cross site teams.
• Must possess good communication skills, be a self‑driven individual, and a good team player.

Personal attributes:

Can‑do attitude. Strong technical leadership attributes. Curious, creative, and good at solving problems. Execution and results oriented. Self‑driven, Thinks Big and is highly accountable. Good communication skills.

The annual salary for this position ranges from $231,100 - $358,200. The actual annual salary offered will depend on several factors, including - among others - job-related skills, experience, technical expertise, qualifications, work location, and business needs. The annual salary range for this position is subject to change and may be adjusted in the future.

In addition to base salary, this role is also eligible for private company equity, and a comprehensive package of employee benefits. Please note that the salary ranges listed for U.S. roles reflect base salary only and do not include equity or other forms of compensation.

EEO Employer:

SiMa is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.