Senior VLSI/ASIC Architect & SoC Design Leader

HP Enterprise; Sunnyvale (CA); Vor Ort; USD 180.000 - 280.000; Vollzeit

Benefits dieser Stelle

Subsidized health insurance

Industry-leading maternity/paternity‑t

Hybrid work model

Annual equity awards

Zusammenfassung

HP Enterprise is seeking an experienced Principle VLSI/ASIC Design Engineer in Sunnyvale, CA, to lead architecture, RTL design, and analysis of complex SoC solutions. The role shapes technology roadmaps, collaborates across teams, and ensures production-ready designs.

The candidate will mentor engineers, influence product strategy, and drive design methodologies while delivering high-performance, scalable ASIC blocks for networking and compute applications.

Qualifikationen

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.

Aufgaben

• Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
• Define architectural approaches, microarchitectures, design methodologies, and implementation plans.
• Design, develop, and modify complex RTL blocks using industry-standard HDLs.
• Drive RTL implementation from architecture through synthesis and timing closure.
• Analyze tradeoffs on performance, power, area, and MTTR.

Kenntnisse

RTL design

ASIC/VLSI architecture

Networking ASICs

High-speed interfaces

Design exploration

Mentoring engineers

Analytical modeling

SystemVerilog

Verilog

Timing analysis

Ausbildung

Electrical/Computer Engineering or CS degree

Tools

Synthesis tools

Formal verification tools

Automation & tooling

Jobbeschreibung

HP Enterprise is seeking an experienced Principle VLSI/ASIC Design Engineer in Sunnyvale, CA, to lead architecture, RTL design, and analysis of complex SoC solutions. The role shapes technology roadmaps, collaborates across teams, and ensures production-ready designs.

The candidate will mentor engineers, influence product strategy, and drive design methodologies while delivering high-performance, scalable ASIC blocks for networking and compute applications.