Senior VLSI/ASIC Architect & RTL Lead — Hybrid

Hewlett Packard Enterprise; Sunnyvale (CA); Hybrid; USD 181,000 - 367,000; Full time

Benefits offered by this job

Health & Wellbeing

Development programs

Inclusive culture

Job summary

Hewlett Packard Enterprise seeks a Principal VLSI/ASIC Design Engineer in California. The role focuses on architecture, RTL design, implementation, and analysis of complex SoCs for networking and compute.

You will influence product strategy and roadmaps, mentor engineers, and drive design excellence. The position requires strong leadership, cross-functional collaboration, and deep expertise in ASIC/VLSI processes with experience in Verilog/SystemVerilog.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• Typically, 9+ years of experience in ASIC, VLSI, SoC, or related hardware design.
• Experience leading architecture and design exploration through RTL implementation and product integration.

Responsibilities

• Lead early-stage ASIC architecture and design exploration for complex networking, compute, and SoC applications.
• Define architectural approaches, microarchitectures, design methodologies, and implementation plans.
• Design, develop, and modify complex RTL blocks using Verilog or SystemVerilog.
• Drive RTL implementation from architectural definition through synthesis and timing closure.
• Mentor engineers and promote design innovation and engineering excellence.
• Collaborate with architecture, hardware, firmware, verification, and manufacturing teams.

Skills

ASIC/VLSI design principles

RTL design (Verilog/SystemVerilog)

Architectural decisions

Leadership and mentoring

Cross-functional collaboration

Education

Bachelor’s or Master’s degree in Electrical/Computer Engineering or related field

Job description

Hewlett Packard Enterprise seeks a Principal VLSI/ASIC Design Engineer in California. The role focuses on architecture, RTL design, implementation, and analysis of complex SoCs for networking and compute.

You will influence product strategy and roadmaps, mentor engineers, and drive design excellence. The position requires strong leadership, cross-functional collaboration, and deep expertise in ASIC/VLSI processes with experience in Verilog/SystemVerilog.