Senior ASIC Design Engineer - High-Perf Networking (Hybrid)

HITEC; Durham (NC); Hybrid; USD 140,000 - 321,000; Full time

Job summary

Hewlett Packard Enterprise is seeking a highly motivated ASIC Design Engineer to join our networking silicon development team in Durham, NC. This hybrid role will involve architecting modules for high-performance networking chips and delivering verified RTL across power, area, and timing targets.

You will write specs, implement using Verilog/SystemVerilog, develop coverage in SVA, and mentor new engineers while collaborating with Physical Design and Verification teams.

Qualifications

• BS in Electrical or Computer Engineering required; Master’s preferred.
• Proven experience architecting high-performance modules for networking ASICs.
• Experience with Verilog/SystemVerilog and coverage based verification.

Responsibilities

• Architect complex modules and subsystems for high-end networking chips.
• Write detailed functional and micro-architecture specs meeting power/area/perf targets.
• Implement design using Verilog or SystemVerilog.
• Create functional coverage/SVA to catch corner-case bugs.
• Ensure power targets via advanced power reduction techniques.
• Collaborate with Physical Design for timing closure and RTL fixes.
• Work with Verification to validate blocks and mentor junior engineers.

Skills

ASIC design

Computer architecture

Analytical skills

Education

Bachelor’s degree in Electrical or Computer Engineering

Master’s degree preferred

Tools

Verilog

SystemVerilog

SVA

Job description

Hewlett Packard Enterprise is seeking a highly motivated ASIC Design Engineer to join our networking silicon development team in Durham, NC. This hybrid role will involve architecting modules for high-performance networking chips and delivering verified RTL across power, area, and timing targets.

You will write specs, implement using Verilog/SystemVerilog, develop coverage in SVA, and mentor new engineers while collaborating with Physical Design and Verification teams.