Senior PLL Design Engineer — RF/SerDes Clock Innovation

Engg; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks PTO

Medical/Dental/Vision/401k

Charitable giving match

Holidays and sick leave

Fertility/adoption support

Job summary

Samsung Semiconductor Inc. in San Jose, CA is seeking a Senior/Staff PLL Designer to create PLLs and clock-generation blocks for RF/SerDes. You’ll model, simulate, and verify performance across process corners, collaborating with digital, layout, and systems teams.

A strong background in LM, noise analysis, and RTL calibration is required. Applicants should have 5+ years of PLL experience with deep sub-micron CMOS and proficiency in Verilog/SystemVerilog, Matlab/Simulink, and IC CAD tools.

Qualifications

• Bachelor’s degree with 5+ years of PLL design experience.
• Master’s degree with 3+ years or PhD with 0 years in related field.
• Deep sub-micron CMOS PLL experience (5nm–28nm) and multiple topologies.
• Strong knowledge of phase noise, jitter, loop dynamics and spurs.
• Proficiency in IC CAD tools and RTL-based calibration.

Responsibilities

• Design PLLs and clock generation circuits for RF/SerDes applications.
• Develop PLL blocks: VCO/DCO, charge pumps, loop filters, PLLs.
• Model, analyze noise/jitter; perform Monte Carlo and silicon correlation.
• Verify design with transistor-level sims and lab bring-up.
• Collaborate with digital/layout teams to meet performance targets.
• Support characterization and debugging of silicon prototypes.

Skills

PLL design

Phase noise

Jitter analysis

Verilog/SystemVerilog

Matlab/Simulink

IC CAD tools

Layout sensitivity

RTL calibration

Education

Bachelor’s degree (related field)

Master’s degree (related field)

PhD (related field)

Tools

Spectre

SpectreRF

AMS simulator

Job description

Samsung Semiconductor Inc. in San Jose, CA is seeking a Senior/Staff PLL Designer to create PLLs and clock-generation blocks for RF/SerDes. You’ll model, simulate, and verify performance across process corners, collaborating with digital, layout, and systems teams.

A strong background in LM, noise analysis, and RTL calibration is required. Applicants should have 5+ years of PLL experience with deep sub-micron CMOS and proficiency in Verilog/SystemVerilog, Matlab/Simulink, and IC CAD tools.