Senior PLL Design Engineer — RF & Clocking

Samsung-Semiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

Charitable matching

4+ weeks PTO

Fertility/adoption stipend

Confidential therapy services

Onsite gym & cafe

Flexible work environment

Job summary

Samsung Semiconductor Inc. (SSI) seeks a Senior/Staff PLL Designer to craft PLLs and clocking subsystems for RF transceivers and SerDes in advanced CMOS tech.

You’ll model, verify, and characterize PLLs, collaborating with digital, layout and systems teams to hit performance, power and area goals. The role requires a Master’s with 2+ years or PhD with 0 years, strong Spectre/SpectreRF/AMS, Matlab/Simulink, and Verilog/SystemVerilog skills, plus lab phase-noise and jitter experience.

Qualifications

• Master’s degree with 2+ years of experience or PhD with 0 years of experience in a related field.
• Experience designing PLLs in deep sub-micron CMOS (5nm-28nm).
• Strong understanding of phase noise, jitter, loop dynamics and fractional spurs.
• Proficiency with IC design CAD tools (Spectre/SpectreRF/AMS).
• Proficient in Matlab/Simulink for modeling and analysis.
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation.
• Experience RTL design and digital calibration concepts.

Responsibilities

• Design PLLs and clock generation circuits for RF and SerDes applications.
• Develop and verify PLL building blocks: VCO/DCO, charge pumps, loop filters, PDs, dividers, and interpolators.
• Model, analyze, and budget jitter and phase noise.
• Collaborate with digital, layout and systems teams to meet performance/power/area targets.
• Support bring-up, characterization and silicon debug in the lab.

Skills

PLL design

CMOS design

Matlab/Simulink

Verilog/SystemVerilog

Lab characterization

RTL design

Layout guidance

Education

Master’s degree in related field

PhD in related field

Tools

Spectre

SpectreRF

AMS simulator

Job description

Samsung Semiconductor Inc. (SSI) seeks a Senior/Staff PLL Designer to craft PLLs and clocking subsystems for RF transceivers and SerDes in advanced CMOS tech.

You’ll model, verify, and characterize PLLs, collaborating with digital, layout and systems teams to hit performance, power and area goals. The role requires a Master’s with 2+ years or PhD with 0 years, strong Spectre/SpectreRF/AMS, Matlab/Simulink, and Verilog/SystemVerilog skills, plus lab phase-noise and jitter experience.