Senior PLL Designer for High-Performance CMOS IP

Samsung Semiconductor; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

Medical/Dental/Vision

401k

Paid time off (4+ weeks)

Job summary

Samsung Semiconductor is seeking a Senior/Staff PLL Designer in the United States to lead the design of high‑performance PLLs and clocking subsystems for RF transceivers, SerDes, and high‑speed I/O.

The role requires 5+ years of hands‑on PLL experience in deep sub‑micron CMOS (5nm‑28nm), strong skills in Verilog/SystemVerilog, MATLAB/Simulink, and IC CAD tools. You will collaborate with multiple teams and participate in silicon bring‑up and characterization.

Qualifications

• Bachelor’s with 5+ years of experience or Master’s with 3+ years of experiences or PhD with 0 years of experience in a related field.
• Extensive hands‑on experience designing PLLs in deep sub‑micron CMOS (5nm‑28nm).
• Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs.
• Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator.
• Strong Matlab/Simulink skills for behavioral modeling and system‑level analysis.
• Familiarity with Verilog/SystemVerilog for mixed‑signal simulation.
• Solid understanding of layout‑sensitive design and ability to guide critical PLL layout (LC tank, charge pump, reference path).
• Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment.
• Experience with RTL design (Verilog/SystemVerilog) to implement PLL‑related digital calibration circuits, including frequency calibration, phase calibration, and background self‑calibration logic.

Responsibilities

• Design PLLs and clock generation circuits (integer‑N, fractional‑N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications.
• Design critical PLL building blocks including VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators.
• Perform PLL system‑level modeling, noise analysis, and jitter budgeting using Matlab/Simulink.
• Drive design verification including transistor‑level simulation, Monte Carlo analysis, and silicon correlation.
• Collaborate with digital, layout, and systems teams to deliver PLL IPs meeting performance, power, and area targets.
• Support bring‑up, characterization, and debug of silicon prototypes in the lab.

Skills

PLL design

Matlab/Simulink

Verilog/SystemVerilog

Problem solving

Communication

Education

Bachelor’s in Electrical Engineering

Master’s in Electrical Engineering

PhD in related field

Tools

Spectre

SpectreRF

AMS simulator

Job description

Samsung Semiconductor is seeking a Senior/Staff PLL Designer in the United States to lead the design of high‑performance PLLs and clocking subsystems for RF transceivers, SerDes, and high‑speed I/O.

The role requires 5+ years of hands‑on PLL experience in deep sub‑micron CMOS (5nm‑28nm), strong skills in Verilog/SystemVerilog, MATLAB/Simulink, and IC CAD tools. You will collaborate with multiple teams and participate in silicon bring‑up and characterization.