Senior Engineer, PLL Design

Engg; San Jose (CA); On-site; USD 138,000 - 206,000; Full time

Benefits offered by this job

4+ weeks PTO

Medical/Dental/Vision/401k

Charitable giving match

Holidays and sick leave

Fertility/adoption support

Job summary

Samsung Semiconductor Inc. in San Jose, CA is seeking a Senior/Staff PLL Designer to create PLLs and clock-generation blocks for RF/SerDes. You’ll model, simulate, and verify performance across process corners, collaborating with digital, layout, and systems teams.

A strong background in LM, noise analysis, and RTL calibration is required. Applicants should have 5+ years of PLL experience with deep sub-micron CMOS and proficiency in Verilog/SystemVerilog, Matlab/Simulink, and IC CAD tools.

Qualifications

• Bachelor’s degree with 5+ years of PLL design experience.
• Master’s degree with 3+ years or PhD with 0 years in related field.
• Deep sub-micron CMOS PLL experience (5nm–28nm) and multiple topologies.
• Strong knowledge of phase noise, jitter, loop dynamics and spurs.
• Proficiency in IC CAD tools and RTL-based calibration.

Responsibilities

• Design PLLs and clock generation circuits for RF/SerDes applications.
• Develop PLL blocks: VCO/DCO, charge pumps, loop filters, PLLs.
• Model, analyze noise/jitter; perform Monte Carlo and silicon correlation.
• Verify design with transistor-level sims and lab bring-up.
• Collaborate with digital/layout teams to meet performance targets.
• Support characterization and debugging of silicon prototypes.

Skills

PLL design

Phase noise

Jitter analysis

Verilog/SystemVerilog

Matlab/Simulink

IC CAD tools

Layout sensitivity

RTL calibration

Education

Bachelor’s degree (related field)

Master’s degree (related field)

PhD (related field)

Tools

Spectre

SpectreRF

AMS simulator

Job description

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.

Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.

Samsung Semiconductor Inc. (SSI) is advancing the world’s technology. As a leader in Memory, System, LSI and LCD technologies, our US teams contribute to breakthroughs in 5G, SOC, memory and display. With our global perspective and diversity of thought, we proudly serve our customers around the world. We are looking for team members who share our commitment to learning and growth and excel when collaborating within and across teams. Samsung Semiconductor Inc is looking for a talented Senior/Staff PLL Designer with strong background and hands-on experience in PLL and clock generation circuit design.

What You’ll Do

• Design PLLs and clock generation circuits (integer-N, fractional-N, digital PLLs, clock multipliers/dividers) for RF and SerDes applications
• Design critical PLL building blocks including VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators
• Perform PLL system-level modeling, noise analysis, and jitter budgeting using Matlab/Simulink
• Drive design verification including transistor-level simulation, Monte Carlo analysis, and silicon correlation
• Collaborate with digital, layout, and systems teams to deliver PLL IPs meeting performance, power, and area targets
• Support bring-up, characterization, and debug of silicon prototypes in the lab

What You Bring

• Bachelor’s with 5+ years of experience or Master's with 3+ years of experiences or PhD with 0 years of experience in a related field.
• Extensive hands-on experience designing PLLs in deep sub-micron CMOS (5nm-28nm), including at least one of: integer-N, fractional-N, digital PLL, or sub-sampling PLL topologies
• Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs
• Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator
• Strong Matlab/Simulink skills for behavioral modeling and system-level analysis
• Familiarity with Verilog/SystemVerilog for mixed-signal simulation
• Solid understanding of layout-sensitive design and ability to guide critical PLL layout (LC tank, charge pump, reference path)
• Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment
• Experience with RTL design (Verilog/SystemVerilog) to implement PLL-related digital calibration circuits, including frequency calibration, phase calibration, and background self-calibration logic
• Excellent problem-solving, analytical, and communication skills

What We Offer

• This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones.
• In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves.
• Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
• Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
• Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
• Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.
• Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
• Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.
• Base Pay Range $138,000 - $206,000 USD

Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where al