Senior Physical-Implementation Lead for AI ASICs

OHO Group (Lithuania); San Francisco (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

OHO Group in San Francisco seeks a Physical Implementation Lead for a stealth startup building an AI-driven chip-design platform. This role owns end-to-end physical implementation for custom ASICs, defining architecture and collaborating with the team while building out your own backend.

You will drive layout strategy, deploy AI-optimisation engines for macro placement, clock and power networks, and tackle design challenges such as IR-drop and thermal-density.

Qualifications

• 5–10 years of physical-design experience with large-die SoCs or compute subsystems.
• Hands-on experience integrating AI-enabled design-optimisation tools into production flows.
• Strong understanding of reinforcement-learning principles and optimization techniques for EDA.
• Proven expertise in physical sign-off including STA, DRC, LVS and EM/IR on advanced nodes.
• Expert-level Python and Tcl for automating infrastructure and layout iterations.

Responsibilities

• Deliver physical implementation for high-throughput, low-latency accelerators, optimized for KPIs.
• Define and drive layout strategy for IP, high-bandwidth interfaces, large SRAM and registers.
• Lead deployment of AI-driven design-optimisation engines to automate macro placement and clock/power networks.
• Address physical-design challenges with AI workloads, including IR-drop and thermal-density mitigation.
• Apply reinforcement-learning principles across backend implementation stages to optimise design.

Skills

Python

Tcl

Reinforcement learning

ASIC/physical-design

Tools

AI-enabled design-optimisation tools

STA/DRC/LVS

Job description

OHO Group in San Francisco seeks a Physical Implementation Lead for a stealth startup building an AI-driven chip-design platform. This role owns end-to-end physical implementation for custom ASICs, defining architecture and collaborating with the team while building out your own backend.

You will drive layout strategy, deploy AI-optimisation engines for macro placement, clock and power networks, and tackle design challenges such as IR-drop and thermal-density.