AI-Driven Physical Design Lead for Advanced SoCs

Alexander Chapman Ltd

San Francisco (CA)

Sur place

USD 180 000 - 260 000

Plein temps

Il y a 33 heures
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Résumé du poste

Alexander Chapman Ltd in San Francisco seeks an experienced Implementation Lead to drive end-to-end physical design of advanced silicon and AI hardware. You will own floorplanning, CTS, routing, and timing closure for high-performance ASICs/SoCs, while pushing AI-driven optimization and automation across large-scale designs.

The role requires 5+ years in physical design, strong scripting (Python/Tcl), and expertise with EDA toolchains.

Qualifications

  • 5+ years hands-on physical design experience.
  • Ownership of complex ASIC or SoC implementations through tape-out.
  • Strong Python and Tcl scripting for PD automation.
  • Experience with advanced-node implementation and EDA tools.
  • Exposure to AI/ML-driven EDA optimization and design-space exploration.

Responsabilités

  • Lead physical implementation of complex ASICs and compute subsystems from floorplanning through tape-out.
  • Own placement, clock tree synthesis, routing, timing closure, and physical sign-off.
  • Develop and optimize implementation methodologies for large-scale designs.
  • Integrate machine learning and automated optimization into PD workflows to improve PPA and efficiency.
  • Address power integrity, thermal, congestion, and timing challenges.
  • Develop scalable automation frameworks to accelerate design iterations and improve quality.

Connaissances

Physical design
ASIC / SoC
Floorplanning
Placement
Clock tree synthesis
Routing
Timing closure
EDA tools
Python scripting
Tcl scripting
AI/ML optimization
Automation frameworks
Power integrity
Thermal analysis

Outils

Synopsys Suite
Cadence Innovus
Mentor Graphics

Description du poste

Alexander Chapman Ltd in San Francisco seeks an experienced Implementation Lead to drive end-to-end physical design of advanced silicon and AI hardware. You will own floorplanning, CTS, routing, and timing closure for high-performance ASICs/SoCs, while pushing AI-driven optimization and automation across large-scale designs.

The role requires 5+ years in physical design, strong scripting (Python/Tcl), and expertise with EDA toolchains.

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