Staff ASIC Implementation Engineer: Timing & Power Optimized

Anysilicon; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Meta’s Silicon Engineering organization seeks a Staff ASIC Implementation Engineer to lead the physical implementation and synthesis of complex custom ASICs for high-performance AI and computing platforms. The role focuses on end-to-end flows, timing closure, and methodology development.

You will collaborate with RTL, architecture, and physical design teams to optimize area, power, and timing while mentoring engineers and driving sign-off readiness for tape-out.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
• 8 years of experience in ASIC implementation, including logic synthesis and timing closure for complex designs.
• Experience with EDA tools such as Synopsys Design Compiler, Fusion Compiler, or Cadence Genus.
• Experience managing synthesis constraints including SDC and UPF.

Responsibilities

• Lead end-to-end ASIC implementation flows, including logic synthesis, static timing analysis, and design-for-test integration.
• Define and own synthesis and implementation methodology, establishing reusable flows and constraints.
• Drive timing closure strategies across hierarchical design partitions, collaborating with RTL designers and physical design engineers.
• Develop and maintain synthesis scripts, constraint files, and automation infrastructure to enhance implementation quality.
• Generate SOC floorplans at various levels and enable block implementation owners to execute on synthesis and physical design.
• Perform top-level logical and physical connectivity analysis for timing and area optimization.
• Partner with architecture and RTL teams to provide feedback on design decisions impacting area, power, and timing.
• Define and enforce design rules and quality sign-off criteria for tape-out readiness.
• Identify and resolve cross-functional implementation risks, communicating status to stakeholders.
• Mentor engineers on implementation methodology and timing analysis techniques.
• Contribute to long-term silicon implementation strategy and evaluate new EDA tools and technologies.

Skills

ASIC implementation

Synthesis methodologies

Scripting for automation

Timing analysis

Education

Bachelor's degree in CS/CE or related field

Tools

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

Job description

Meta’s Silicon Engineering organization seeks a Staff ASIC Implementation Engineer to lead the physical implementation and synthesis of complex custom ASICs for high-performance AI and computing platforms. The role focuses on end-to-end flows, timing closure, and methodology development.

You will collaborate with RTL, architecture, and physical design teams to optimize area, power, and timing while mentoring engineers and driving sign-off readiness for tape-out.