Senior Physical Design Signoff Engineer - Timing & Power

Mirafra Technologies; Mountain View (CA); On-site; USD 160,000 - 210,000; Full time

Job summary

Mirafra Technologies is seeking an experienced Physical Design Signoff Engineer to drive timing, signoff closure, and power integrity for advanced-node ASIC/SoC designs. The role requires hands-on work with Fusion Compiler, PrimeTime, RedHawk, and Calibre to ensure robust tapeout readiness.

You will coordinate with PD, STA, synthesis, RTL, library and foundry teams to resolve signoff issues and validate methodologies, constraints, and ECO implementations across full-chip and block-level signoff.

Qualifications

Responsibilities

• Own physical design signoff and closure from post-route through tapeout.
• Perform STA signoff using Synopsys PrimeTime across multiple PVT corners and modes.
• Analyze and resolve setup/hold violations, max transition, capacitance issues, clock skew and latency, timing exceptions and unconstrained paths, SI/crosstalk violations.
• Work with PD team using Fusion Compiler to drive timing, congestion and physical closure.
• Perform IR-drop and EM analysis using Ansys Apache RedHawk and analyze power distribution and EM violations.

Job description

Mirafra Technologies is seeking an experienced Physical Design Signoff Engineer to drive timing, signoff closure, and power integrity for advanced-node ASIC/SoC designs. The role requires hands-on work with Fusion Compiler, PrimeTime, RedHawk, and Calibre to ensure robust tapeout readiness.

You will coordinate with PD, STA, synthesis, RTL, library and foundry teams to resolve signoff issues and validate methodologies, constraints, and ECO implementations across full-chip and block-level signoff.