STA & Timing Signoff Engineer - MMMC & FinFET Expert

Central Business Solutions, Inc; Santa Clara (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Central Business Solutions, Inc. is seeking a Static Timing Analysis Engineer to own timing signoff for advanced SoC designs. You will drive constraints, perform MMMC timing closure, and collaborate with physical design, synthesis, DFT teams to deliver silicon-ready timing.

The ideal candidate has strong fundamentals in STA, hands-on PrimeTime, SDC, and parasitic extraction, with 3–8 years in STA or physical design, in a multi-node FinFET environment.

Qualifications

• Strong fundamentals in static timing analysis including setup/hold and derating concepts.
• Hands-on experience with Synopsys PrimeTime / PrimeTime SI for timing signoff.
• Proficiency in SDC constraint development, debug, and validation.
• Experience with MMMC analysis.
• Understanding of OCV / AOCV / POCV variation-aware timing.
• Knowledge of crosstalk / signal integrity.
• Familiarity with SPEF extraction and RC corners.
• Understanding of physical design flow and timing interaction.
• Exposure to advanced technology nodes (16nm/7nm/5nm/3nm FinFET).
• Scripting in TCL; Python or Perl for automation.
• Strong debugging and cross-functional collaboration.

Responsibilities

• Develop and maintain timing constraints (SDC), clock definitions and I/O delays.
• Perform block-level and full-chip timing signoff across MMMC setups.
• Analyze and close setup/hold violations and generate ECOs with P&R coordination.
• Run SI analysis and resolve crosstalk violations; correlate with extraction.
• Set up RC parasitic extraction and SPEF; ensure signoff correlation.
• Apply variation-aware timing methodologies for robust margins.
• Build timing abstracts and interface models for hierarchical designs.
• Handle UPF-based multi-voltage timing checks in complex flows.
• Automate timing analysis and ECO flows using TCL/Python.
• Collaborate with Synthesis, P&R, CTS, DFT, and IR/EM teams; present reviews.

Skills

Static timing analysis

SDC constraint development

MMM C analysis

OCV/AOCV/POCV timing

TCL scripting

Crosstalk analysis

P&R interaction

Timing signoff

Debugging and collaboration

Education

Bachelor’s in ECE/EEE/VLSI

Tools

PrimeTime

PrimeTime SI

StarRC

Quantus QRC

Cadence Tempus

Job description

Central Business Solutions, Inc. is seeking a Static Timing Analysis Engineer to own timing signoff for advanced SoC designs. You will drive constraints, perform MMMC timing closure, and collaborate with physical design, synthesis, DFT teams to deliver silicon-ready timing.

The ideal candidate has strong fundamentals in STA, hands-on PrimeTime, SDC, and parasitic extraction, with 3–8 years in STA or physical design, in a multi-node FinFET environment.