Physical Design Manager

Quest Global; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Quest Global in San Jose, CA seeks a highly experienced Physical Design Manager to lead end-to-end ASIC physical design from RTL to tape-out. The role requires hands-on mastery of advanced-node implementation, timing closure, and sign-off flows.

You will drive Place & Route, CTS strategies, and clock-tree design, manage congestion, and mentor engineers to meet aggressive PPA targets. Strong Cadence Innovus experience is mandatory and tape-outs are essential.

Qualifications

• 12+ years of relevant experience in ASIC/SoC Physical Design.
• Strong leadership and communication skills to guide teams.
• Experience delivering tape-outs and working with sign-off flows.

Responsibilities

• Lead and execute end-to-end Physical Design implementation for complex SoCs and ASICs.
• Drive timing closure through advanced STA methodologies and optimization.
• Own Place & Route activities, congestion management, and design optimization.
• Develop CTS strategies, clock tree design, and skew management.
• Mentor junior engineers and drive technical decisions.

Skills

Leadership

Mentoring

Communication

Problem-solving

Scheduling

Education

Bachelor's Degree in Electrical Engineering

Tools

Cadence Innovus

Job description

We are looking for a highly experienced Physical Design Manager to lead and execute complex ASIC physical design activities from RTL to Tape-out. The ideal candidate will have extensive hands-on expertise in advanced-node physical implementation, timing closure, physical verification, and methodology development. Strong proficiency in Cadence Innovus is mandatory and non-negotiable.

Location : San Jose,CA

Key Responsibilities :

• Lead and execute end-to-end Physical Design implementation for complex SoCs and ASICs.
• Perform RTL setup, synthesis, and optimization to achieve Power, Performance, and Area (PPA) targets.
• Drive timing closure through advanced STA methodologies and optimization techniques, including top-level timing analysis.
• Execute and analyze EM/IR verification to ensure robust silicon implementation.
• Own Place & Route activities, congestion management, and design optimization.
• Develop and implement Clock Tree Synthesis (CTS) strategies, including custom clock tree design, skew balancing, and insertion delay reduction.

Mandatory Skills

Strong hands-on expertise with Cadence Innovus (Mandatory / Non-Negotiable)

Full-chip Physical Design experience from RTL to Tape-out

Top-level STA and Timing Closure expertise

Floorplanning, CTS, Place & Route, Physical Verification

EM/IR Analysis and Sign-off Flows

Preferred Qualifications

• Expertise in industry-standard EDA tools and implementation methodologies.
• Experience with advanced technology nodes and complex SoC designs.
• Excellent problem-solving, leadership, and communication skills.
• Ability to mentor junior engineers and drive technical decisions.

Education & Experience

• Bachelor's Degree in Electrical Engineering, Electronics Engineering, or related field.
• 12+ years of relevant experience in ASIC/SoC Physical Design.
• Proven track record of delivering successful tape-outs.