Physical Design Engineer — RTL to Tapeout, Relocation

Insight Global; Colorado Springs (CO); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Relocation package

Annual bonus (up to 20%)

Employee Stock Purchase Program (ESPP)

RSU package

Comprehensive health benefits (medical

Dental and vision plans

401(k) with company match

Paid holidays

Paid sick leave and vacation

Job summary

Insight Global is seeking two Physical Design Engineers to join a leading semiconductor company in Colorado Springs or San Jose. The role covers RTL-to-silicon tape-out, requiring deep knowledge of synthesis, verification, and timing closure across complete PD flows.

You will collaborate with RTL engineers and IC designers on floorplanning, layout, P&R, and clock-tree synthesis, contributing to AI/ML PCIe switch and enterprise storage products.

Qualifications

• Bachelor’s degree required, electrical/electronics engineering preferred.
• Full physical design cycle experience from RTL to tape-out; GDSII experience is a plus.
• TCL/Perl scripting experience for flow automation.
• Experience with floor planning, layout, place-and-route, and timing closure.

Responsibilities

• Execution of Physical Design, Synthesis, Physical Verification, and Timing Closure
• Setup and Synthesizing RTL
• Timing closure through various methods and strategies
• EM/IR Analysis
• Place and Route
• Clock Tree Synthesis
• Floor-planning and Layout
• Flow and Methodology Development
• Collaborating with IC Design RTL Engineers

Skills

Physical Design

Synthesis

Physical Verification

Timing Closure

Place and Route

Floorplanning

Clock Tree Synthesis

RTL-to-Tape-out

RTL Scripting (TCL/PERL)

Education

Bachelor's degree in Electrical/Electronic Engineering

Master's degree in Electrical/Electronic Engineering

Tools

GDSII

Job description

Insight Global is seeking two Physical Design Engineers to join a leading semiconductor company in Colorado Springs or San Jose. The role covers RTL-to-silicon tape-out, requiring deep knowledge of synthesis, verification, and timing closure across complete PD flows.

You will collaborate with RTL engineers and IC designers on floorplanning, layout, P&R, and clock-tree synthesis, contributing to AI/ML PCIe switch and enterprise storage products.