ASIC Physical Design Engineer (New Grad) - Equity & Bonus

Broadcom, Inc.; San Jose (CA); On-site; USD 83,000 - 132,000; Full time

Benefits offered by this job

Discretionary bonus

Equity grants/awards

Medical, dental and vision plans

401(k) with company matching

ESPP

Job summary

Broadcom, Inc. in San Jose, CA, is seeking a Physical Design Engineer (NCG) to contribute to high-performance ASIC design. You will assist in block-level floorplanning, placement and routing, and clocking strategies for next-gen networking and AI accelerators.

The role emphasizes STA, timing closure, signoff, and signoff-automation in cutting-edge 3nm/2nm nodes, with opportunities for hands-on growth and collaboration across a world-class team.

Qualifications

• Bachelor's or Master's in Electrical Engineering or Computer Engineering with recent graduation.
• Hands-on coursework or projects using EDA design tools such as Cadence/Synopsys/Siemens.

Responsibilities

• Participate in block-level floorplanning and run P&R flows with industry EDA tools.
• Perform STA, debug timing paths and implement ECOs for timing closure.
• Run physical verification checks (DRC, LVS, ERC, Antenna) and fix signoff issues.
• Analyze IR drop and electromigration to ensure power grid integrity.
• Develop and maintain automation scripts (TCL, Python, Ruby) to improve flow efficiency.

Skills

Digital CMOS logic design

STA concepts

Scripting (TCL, Python, Ruby, Bash)

Debugging and problem solving

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree in Electrical or Computer Engineering

Tools

Cadence Innovus/Tempus

Synopsys IC Compiler II/PrimeTime

Siemens tools

Job description

Broadcom, Inc. in San Jose, CA, is seeking a Physical Design Engineer (NCG) to contribute to high-performance ASIC design. You will assist in block-level floorplanning, placement and routing, and clocking strategies for next-gen networking and AI accelerators.

The role emphasizes STA, timing closure, signoff, and signoff-automation in cutting-edge 3nm/2nm nodes, with opportunities for hands-on growth and collaboration across a world-class team.