Principal Physical Design Engineer

8413 LSI Corporation; San Jose (CA); Sur place; USD 144 000 - 230 000; Plein temps

Avantages offerts par ce poste

Medical, dental and vision plans

401(k) matching

ESPP

Employee Assistance Program

Paid holidays

Paid sick leave and vacation

Résumé du poste

Broadcom, Inc. in San Jose, CA seeks a Principal Physical Design Engineer to lead block-level floorplanning, P&R, CTS, and signoff for high-performance networking and AI ASICs. You will drive complex tapeouts on cutting-edge nodes and collaborate with multi-disciplinary teams.

You will own end-to-end physical design flows from floorplanning to GDSII, optimizing timing, power, and SI across 5nm–2nm processes, using Cadence Innovus, PrimeTime, StarRC, and Calibre, while mentoring junior engineers.

Qualifications

• BS or MS in Electrical/Computer Engineering or related field.
• 12+ years of hands-on physical design experience taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
• Experience tapeouts on TSMC N7/N5/N3 or equivalent foundry processes.
• Proficiency in P&R: Cadence Innovus; Timing/STA: PrimeTime or Tempus; Extraction & IR/EM: StarRC/QRC, RedHawk; DRC/LVS: Calibre.
• Automation: TCL, Python, and Unix shell scripting for flow automation.
• Excellent technical leadership and cross-functional communication.

Responsabilités

• Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus.
• Drive floorplanning, placement, CTS, routing, and timing/power optimization on 5nm, 3nm, 2nm nodes.
• Perform MCMM STA, SI optimization, and power grid optimization for signoff using PrimeTime, Voltus, or RedHawk.

Connaissances

Technical leadership

Problem solving

Cross-functional collaboration

Automation scripting

Unix shell scripting

Formation

B.S./M.S. in Electrical or Computer Engineering

Outils

Cadence Innovus

Synopsys PrimeTime

Cadence Tempus

StarRC

QRC

RedHawk

Calibre

Description du poste

About the Role

Broadcom’s ASIC Products Division (APD) is looking for a Principal Physical Design Engineer to lead physical design implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will drive complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14).

Key Responsibilities

• Full-Flow Implementation: Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus
• Execution: Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes (5nm, 3nm, 2nm) using multi-patterning and complex metal stacks.
• Timing & Power Closure: Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization (static/dynamic IR-drop, EM) for signoff using PrimeTime, Voltus, or RedHawk.

Qualifications & Requirements

• Education: B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience: 12+ years of hands‑on physical design experience successfully taping out complex high‑frequency, ultra‑large‑scale networking or AI ASICs.
• Deep Sub‑Micron Expertise: Direct experience executing tapeouts in TSMC advanced nodes (N7, N5, N3) or equivalent foundry processes.
• EDA Tool Mastery: High proficiency in major physical design tool flows: P&R: Cadence Innovus; Timing/STA: Synopsys PrimeTime or Cadence Tempus; Extraction & IR/EM: StarRC / QRC, RedHawk; DRC/LVS: Siemens Calibre.
• Automation Skills: Advanced TCL, Python, and Unix shell scripting for flow automation and database manipulation.
• Communication: Excellent technical leadership, problem‑solving, and cross‑functional communication skills.

Preferred Qualifications

• Strong background in high‑speed clock network implementation (H‑tree, mesh, low‑power CTS).
• Experience with power‑aware implementation flows (UPF/CPF, multi‑voltage domains, clock/power gating).

Compensation and Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00. As a valued member of our team, you’ll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company’s growth. All subject to relevant plan documents and award agreements.

• Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time.
• The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Equal Opportunity Statement

Broadcom is proud to be an equal opportunity employer.

We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.

We will also consider qualified applicants with arrest and conviction records consistent with local law.

Location Information

Location: San Jose, CA

Position Type: Full-Time

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Additional Company Information

We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

For more information please visit our video library and check out our Connected by Broadcom series.